Research Of 3D TLC NAND Flash Channel Model And Program Scheme

NAND Flash memory is a main type of non-volatile memory and it has been widely adopted from mobile consumer devices to enterprise data centers due to its high storage density,low power consumption,low cost-per-bit and high resistance to shock.With the development of process technology in semiconductor,the feature size of NAND Flash memory shrinks continually.Multi-Level technology and 3D stack technology have become dominant in NAND Flash memory,and 3D TLC NAND Flash memory has occupied most of consumer NAND Flash memory market.While,there are various kinds of noises in 3D TLC NAND Flash memory,which affect the reliability of data severely.Progarm interference noise and data retention noise are two dominant sources of data errors in 3D TLC NAND Flash memory.In order to investigate the effect of progarm interference noise and data retention noise in 3D TLC NAND Flash memory,we measure and model the threshold voltage distribution of 7 voltage state based on FPGA NAND Flash memory testing platform and analyze the feature of channel model.Furthermore,to investigate the influence of P/E cycles and data retention noise on data errors,we perform an experiment on flash chips to obtain channel model of 3D TLC NAND Flash memory under different P/E cycles and high temperature retention time.According to the characteristic of program interference errors and retention errors in3 D TLC NAND Flash memory,and the feature of errors distribution in triple-level cell,we propose noval retention errors reduction program sequence scheme to enhance data lifetime of 3D TLC NAND Flash.The experimental results show that applying proposed retention errors reduction program sequence scheme can reduce retention errors significantly compared with conventional program sequence schemes.Data retention time can be extended by87.6%,47.1%,53.3%,and 66.3 % respectively,under 500,1500,2500 and 3500 P/E cycles compared with previous program sequence scheme.