Implementation Of Super-FEC Based On ISDB-T Standard

With the rapid development of Digital information technology,Digital Television(DTV)has completely replaced analog Television.Image quality is one of the most important indicators to measure the performance of digital TV.As is known to all,in the actual transmission process of information,due to the channel transmission characteristics are not ideal and the influence of noise,the data received by the receiver will inevitably have errors,which will lead to the image jumping,discontinuous and the emergence of Mosaic and other phenomena.To solve this problem,the researchers proposed to encode the data using Forward Error Correction(FEC)technique.The FEC technology is adopted in the world's mainstream digital TV standards for channel coding.ISDB-T standard is one of the world's three major digital TV standards based on the ground transmission system.Its channel coding adopts the cascade coding of outer RS code and inner convolutional code,and interleaved technology is added in the middle of outer and inner codes.Firstly,the FEC standard of ISDB-T channel coding is studied.The general method of FEC encoding part is relatively fixed and applied to the video transmitter.The core of channel codec is FEC decoding,and its difficulty often determines whether this coding system can be widely used.In this design,Viterbi probabilistic decoding is used to realize the decoding of convolutional codes,Modified Euclid-Chien-Forney algorithm is used to realize RS decoder,and RAM partitioning cyclic shift method is used to realize interleaver and uninterleaver.In order to improve the performance of channel codec to a greater extent,the standard interleaver and Viterbi decoder are modified on the basis of the traditional FEC decoding process.By adding an iteration operation,Super-FEC with stronger error correction ability is realized.In the FEC hardware design,RS decoder,interleaver/deinterleaver and Viterbi decoder are all adopted pipeline mechanism,which greatly improves the efficiency of decoding.In the convolutional interleaver,the FIFO and some registers needed in the module are replaced and optimized by the design of single port RAM,which saves the module's area consumption.Viterbi decoder adopts the truncated decoding method,which greatly improves the efficiency of decoding without affecting the accuracy of decoding.And for Viterbi decoding design of dual port RAM,the decoder can be pipeline operation.In this paper,the specific sequence of input of all modules is verified by functional simulation,and the correct simulation results are obtained.Finally,the performance simulation of Super-FEC is carried out,and the results show that the Super-FEC system has a better performance than the FEC system.