Back-end Design Of GPU Chip's Sub-module Based On 7nm CMOS Process

The integrated circuit industry has developed rapidly since the 21st century.The technology of Integrated circuit continuously pursue higher performance indicators and better reliability.The process feature size is continuously reduced,and the back-end design of integrated circuits also faces more and more severe challenges.The new process feature which has brought new design rules and more influencing factors need to be considered promots the update of the back-end process.In the 7nm process,on the one hand,the connection delay problem under the deep nanometer size and the complicated clock tree make it more difficult to meet the timing enclosure.On the other hand,higher unit integration and more complex interconnects increase the difficulty of routing which is easier to cause congestion problems and design rule check violations.This paper originated from the intern company's project and completed back-end design of sub-module on a high-performance GPU based on the 7nm process.The results achieved by thsdid are as follows:This thesis completed the placement and routing of the sub-module of the 7nm process graphics chip,including floorplanning,placement,clock tree synthesis and routing.In the floorplanning stage,according to the design rules provided by the process manufacturer and the data flow relationship between sub-modules in the chip and the relevant parameters of the sub-module itself,the placement of macros,the power network and insertion of physical cells are completed.In the placement stage,the scan chain is reorganized and the placement of standard cell is completed.At the same time,referring to the timing estimation report,area utilization heat map and congestion estimation results,the floorplan is manually adjusted and commands are added to control tools to place the standard cells.The clock tree synthesis of the module is completed in the clock tree synthesis stage,the synthesized clock tree is evaluated according to the clock tree synthesis results and timing analysis report,and clock gating technology is used to reduce power consumption.In the routing phase,the routing of the module is completed.In the ECO stage,the violations left in the P&R stage are repaired,and the sub-module is checked for design rules,physical rules and formal verification,and repaired for the problems that occurred.This paper studies the new technologies that have emerged in the 7nm process to solve new technical difficulties:the new photolithography process,Double-Patterning technology,the new design rules it brings and the impact on the back-end process.The MCMM STA method can perform a full-scale parallel analysis of the design timing results.The new Advanced On-Chip Violation model is used to simulate the impact of on-chip violation on timing,which is more accurate than the previous On-Chip Violation model.This paper also analyzes and fixes the problems of the design in P&R stage.In view of the high utilization area in placement stage,the restricted area of placement is reasonably set up.Different design rule violations in routing stage are analyzed and checked and fixed base on the timing reports,congestion maps,utilization maps and design rules check reports.These violations are repaired by adding routing constraints and modifying unreasonable constraints.The sub-module in this design has an area of 1,551,250.71368)~2(1468.328)×1056.488)),the maximum frequency reaches 1.55GHz,and the scale reaches 890,000gates.Through the research of this subject,combined with the actual design situation,it provides new ideas for solving the cell placement problems,congestion problems and violations in ECO stage encountered in the back-end design,and provides some references for the development of domestic integrated circuit back-end design.