Design And Realization Of SAR A/D Converters In Nanoscale CMOS Process

A/D converters have been widely used as the SoCs'fundamental building blocks. With the silicon feature dimension downscaling into nanoscale, great improvement has been made in the performance of digital circuits, but making high performance analog circuits design increasingly difficult. As typical mixed signal circuits, A/D converters are facing both opportunities and challenges to realize high performance based on nanoscale CMOS. SAR A/D converter is one of the most popular ADCs due to its simple architecture, small area and easiness to be integrated with other blocks. SAR ADC contains less analog circuits and has advantages over other ADCs along with CMOS technology downscaling.Based on different types of SAR A/D converter, the passive components'mismatch and energy dissipation of internal D/A conversion networks is explored with theoretical derivation and verified by modeling using Matlab. The key design techniques for the comparators, switches and voltage references in SAR ADCs are discussed in detail. Two A/D converters suitable for different applications are designed and implemented in nanoscale CMOS process.An 8-channel 12-bit 200kS/s touch screen SAR ADC is realized based on SMIC 65nm CMOS low leakage process. The chip size is reduced to be less than 0.13mm~2 by using a novel R-C hybrid D/A conversion network, in which the resistor string is reused by a binary-ratioed capacitor pair. Without adding any additional control logic, a novel offset cancellation technique compatible with the operation of SAR ADC is proposed to reduce the offset of the pseudo-differential comparator. A novel temperature compensation technique used for the ADC internal bandgap voltage reference is proposed. With the double-end piecewise nonlinearity correction method, logarithm cancellation technique and the mixed mode output, the temperature stability of the internal voltage reference is improved. The measurement results of this 12-bit ADC show that the SNDR (Signal to Noise and Distortion Ratio) is 70.13dB and its power dissipation is only 2.8mW, meeting the requirement of the touch screen SoC application.An 8-channal 10-bit SAR ADC is realized based on SMIC 90nm CMOS Logic process. A novel voltage level-shifter suitable for high-speed and low power SoC is described. Compared with traditional one, this level-shifter can operate at higher speed and dissipate even less power. By taking this new level-shifter, together with the optimization on speed of the low-offset pseudo-differential comparator and the internal R-C hybrid D/A conversion network, the 10-bit ADC can operate in a sampling rate of up to 2.5MS/s. This SAR A/D converter occupies an area of 0.051mm2. Under the condition of 3.3V analog supply, 1.0V digital supply and a 100 kHz 3.0Vp-p sinusoidal input signal, the ENOB (Effective Number of Bits) of this ADC is measured to be 9.41 and the power dissipation is 6.62mW.Operated with two power supplies, both of these two nanoscale ADCs achieve high SNDR with small area. The FoM (Figure-of-Merit) of these two converters are 5.32-pJ/conv. step and 4.47 pJ/conv. step respectively, which are at the advanced level in this direction.