NoC High-speed Communication Architecture Design

In recent years,with the rapid development of large-scale integrated circuits and 5G communication technology,the performance requirements for System on Chip(So C)have become higher and higher,but the on-chip multi-core system has many problems of its own and bottlenecks in technological development.It is becoming more and more difficult to make up for related bottlenecks through Integrated Circuit(IC)design and process,so it is a good choice to design from a new architecture.Network on Chip(NoC)has irreplaceable advantages over traditional So C structures in ultra-large-scale,high-density integrated circuits.Although there have been more and more researches on NoC in recent years,high-tech fields such as chip design have been Blocked by foreign monopolies,domestic research on high-speed,high-bandwidth,and low-latency NoC systems is also rare,and there are no successful application examples.Therefore,this article specifically designs a general-purpose NoC high-speed communication architecture for high-speed,high-bandwidth,and low-latency systems.NoC high-speed communication architecture mainly includes two parts,one is the high-speed router part,and the other is the cache controller part.The high-speed router determines whether the NoC system can have a higher bandwidth and ultra-low latency.Through in-depth research on the basic router micro-architecture,on this basis,the structure of the router is optimized,the internal bus communication method is changed,and the clock frequency is increased.,Increase the data bit width,select the appropriate routing algorithm,simplify the cache mode and arbitration mechanism,and finally design a router with high bandwidth and low latency.In high-speed transmission systems,large-capacity memory is needed to buffer burst data.The internal memory capacity of the chip is limited and often cannot meet the design requirements,and a large-capacity external memory must be used.Therefore,the NoC high-speed communication designed in this article also requires a large-capacity external memory,so a dedicated cache controller must be designed and mapped as a NoC resource node.The NoC high-speed communication architecture designed in this paper makes full use of the advantages of NoC technology and expands the communication bandwidth and rate of the NoC system.This architecture can be used in a high-speed data acquisition system with multiple ADC interleaved sampling,and it is also suitable for multi-channel video stream acquisition and transmission.system.Finally,through the Vivado synthesis tool and Model Sim simulation tool,detailed verification and performance analysis of the NoC high-speed communication architecture as a whole and the sub-modules of the design are carried out.The verification work can be used for the related design of the high-speed data acquisition system.