The Research Of ECC Based On LDPC For Applications In Solid State Disk Drive

As Solid-State Drive storages based on NAND Flash feature on high performance and low power consumption,they have been successfully applied in many fields,such as military field,car even navigation,which seems to be the development trend of storage system.Nowadays flash technology reaches 25 nm or even below 25 nm and its structure changes from SLC to MLC even TLC,flash storage capacity of one cell has been improved for serval times.However,raw bit error rate increases a lot within flash storage.What's more important is that current error correction technology still depends on traditional ECCs which are beyond SSD storage characteristic so that it's hard to make full use of SSD's high performance.Because of its powerful random error correction and fast parallel decoding speed of Low-density parity-check code(LDPC),it's been applied in storage area.However,due to inherent features of SSD Storage,like high coding rate and low volume,applications in storage field meet some challenges.To suit for random errors in SSD,new technology based on LDPC code was developed.This paper mainly focuses on the following aspects:1.First of all,this paper presents an algorithm called dominating error region bit-flipping based on dominating error region,which is not only fit for SLC-SSD,but also for MLC-SSD.It provides solutions to restricting the occurrences of even number of flipped bits and bit-error propagations.Simulations show that the proposed algorithm can effectively enhance error correction ability as well as greatly prompt decoding speeds for bit-flipping algorithms.2.On this foundation,by constructing multiple reads model for SSD based on Gaussi channel,proposed strategy attain explicit channel information among different SSD life stats.then optimum value q for error region is got by maximize mutual information based on that model.At last,many experiments have been conducted to verify whether that theory is correct.The outcome of experiments has showed the consistence with the proposed theory about how much q should choose during SSD different lifetime.3.Finally,the key circuit about error correction region is implemented on FPGA.At the low consumption of implementation of error region circuit,the proposed algorithm suits for real applications.More importantly,proposed algorithm is very convenient to combine and benefit with other bit-flipping algorithms.