A Study Of Neural Branch Predictor

As the demand for high performance applications processors increases, superscale and deeper pipeline has now become the mainstream technology in embedded processor. However, conditional branches in the program have become the main reasons of undermining the continuous operations in superscalar and deep pipeline processor. Pipeline performance loss caused by the conditional branches instruction restricting processor performance has become a major bottleneck in processor design. In order to reduce the performance loss in pipeline caused by conditional branches, branch prediction is widely used in modern processors. Branch prediction technology, which has experienced the development of 2bit branch predictor, global / local history branch predictor, Gshare branch predictor and neural branch predictor, is now maturing. To search for further constraining factor in branch prediction accuracy, this paper studies the relationship between the function call and the branch prediction in the theoretical and experimental. The main contents are as follows:First, sum up the domestic and international development direction of this branch prediction. Problems and how to resolve the problem are showed in the all stages of branch prediction development process. The introduction also focuses on the neural network branch predictor and efforts in the current branch prediction to improve accuracy. Research direction is proposed.Second, through in-depth analysis of function call and return, point out the alias in the process of function call and return. Discrete function call is proposed as a solution to eliminate branch alias. A more efficient simulation platform is proposed to test the algorithm. The experiment result shows that the discrete function call method in branch prediction can really improve the branch prediction accuracy. Then, in application background of CKCORE processor, the neural branch predictor with discrete function call has been implemented in hardware and verified through system verilog verification platform. The challenge of case management in n platform caused by complex hardware design is discussed .Finally, the summary of text is given. Discuss the improvement direction of the existing algorithm.