RSA Algorithm Optimization And Chip Design For Digital Signature

With the rapid development of the Internet and communication technology in recent years,the field of information security is facing unprecedented challenges.In the process of communication between the two parties on the Internet,digital signature technology is often used to verify the authenticity of information and prevent counterfeiting.As a commonly used public key algorithm in digital signatures,the RSA algorithm can perform identity verification while encrypting data,and has the advantages of good security and easy implementation.In the new national secret standard in 2018,it is clearly required that the key length of the RSA algorithm used for digital signatures needs to reach 2048 bits,and the RSA algorithm under this requirement has low computational efficiency and high hardware overhead due to the substantial increase in key length.problem.Therefore,designing an RSA encryption chip that meets national secret standards,has high computing speed and low hardware overhead is of great significance to the promotion and application of digital signatures.This paper focuses on the problems of long operation time and high hardware overhead of traditional RSA algorithm under 2048-bit key length.A two-layer pipelined RSA encryption hardware architecture is designed.This structure supports the AMBA 4.0 bus protocol and has high-speed,configurable advantage.In the algorithm optimization,this paper starts with the selection of prime numbers,introduces the Miller-Rabin algorithm to select prime numbers on the basis of the four prime number RSA optimization algorithm,and solves the time-consuming problem of the modulus n generation process;it is proposed on the basis of the original Montgomery algorithm A modular exponentiation algorithm optimization scheme with pseudo-random and exponential mask operations is added,which can successfully resist power consumption attacks and fault attacks while increasing the calculation speed.In terms of hardware implementation,in this thesis uses AXI bus as the system bus,and configures external registers to meet the working mode of the RSA algorithm at two key lengths of 1024bits and 2048bits;a double-layer pipeline structure is used in the modular multiplication unit.The layer adopts an 11-stage pipeline design,and the outer layer adopts a 6-stage pipeline design,so that the circuit has a higher operating speed and clock frequency.This paper is based on the hardware description language Verilog HDL for RTL-level design,the implementation environment is Vivado 2019.1,and the software-assisted method is used to complete the simulation verification of the functional modules.Then,the FPGA verification was completed on the XC7A200T-2FBG676I development board,and the RSA hardware circuit designed in this article was realized by ASIC with SMIC 180nm process.The experimental results show that the time to complete an RSA algorithm operation under the key length of 1024bits and 2048bits is as low as 3.6ms and 15.0ms,respectively.In the 2048bits working mode,the total dynamic power consumption of the system is 33.7m W and the realization area is 2.09mm~2,which is similar to similar Compared with the RSA chip,it has the advantages of fast computing speed and low hardware overhead,conforms to the national secret standard,and can meet the needs of digital signatures.