Public Key Cryptography Algorithm Research And Main Modules Design And Verification

With the rapid progress of computer and internet technology, information networks have become an important guarantee for the development of today's society. Networking information security is increasingly becoming a major issue of national security and social stability. Science and technology of cryptograghy is becoming a hot research in the field of information security, so, the research of public key cryptograghy chip has immediate practical significance. In this paper, DH, RSA and other algorithms which are widely used in the field of public-key cryptograghy have been studied deeply. Modular multiplication and exponentiation algrotithm were summed up as a common key module for the public-key cryptograghy. Hardware design and verification for these key modules was focused on.In the design, A new radix-4 Montgomery modular multiplication and the optimized circuit architecture were proposed. Iterations can be reduced by about 50% compared to the traditional algorithm. Based on this module, the implementation of modular exponentiation module follows completely parallel modular exponentiation flow to avoid self-improvement chain and the repeated interim output/output format conversion, significantly improves the efficiency of modular exponentiation operations. Based on these key data path modules, the control units of modular multiplication and exponentiation, on-chip memory module, input and output interface module .ect were designed to form a complete public key cryptograghic algorithm processing system.In the fuctional verification, VMM modern verification architecture based on SystemVerilog was used to built hierarchical verification platform, introduce Constrained-Random Tests(CRT) generation, coverage, assertion, VIP validation element, and other advanced verification methods, develop test cases of each module, complete functional verification. At the same time, the definition of function points were refined based on the coverage properties and coverage groups.Finally, the simulation examples, synthesis results and performance analysis were proposed in the RSA cryptographic algorithm application. The optimization is technology independent and thus should suit well for not only FPGA implementation but also ASIC. This design can complete a standard 1024-bit RSA encrypt operation with only 9836 clock cycles. Compared to the recently proposed design in the literature, the proposed design can achieve an increase of over 50% in throughput.