Research And Design Of RSA Public-Key Cryptographic Coprocessor

RSA cryptosystem is currently one of the best known and most widely used in public key cryptosystems, and the core arithmetic of RSA is modular exponentiation which bases on large number modular multiplications. The security of this system depends on the size of the encryption/decryption key. With the improvement of the attack technology, in order to protect the system from attacking, it is necessary to choose a longer key with complicated cryptography algorithm. When the key size is longer than data width of the modular multiplication circuit, the original chip has to be redesigned. Based on research of expandable modular multiplication, the thesis designs a RSA cryptography chip can implement encryption operation with expandable key.The thesis proposes an expandable JB algorithm based word operation and an improving Hybrid algorithm, and we get an expandable Hybrid algorithm by combining the expandable Montgomery algorithm. The expandable Hybrid algorithm can speed up the performance of modular multiplication to be doubled by partitioning operand for combining the expandable JB and the expandable Montgomery algorithms to operating both in parallel. Based on the expandable Hybrid algorithm with alterable parameter, we designe an expandable RSA modular exponent circuit which can satisfy arbitrary security degree demands by supporting arbitrary key size if resource can be enough.The thesis implements and testes the expandable RSA modular exponent circuit that can be extended to 2048 bits in Stratix II EP2S30F672C3 FPGA of Altera company, at the utmost clock frequency of 112.69 MHz, the speed of 512/1024/2048 bits encryption or decryption rate is respectively up to 337.7Kbit/s, 189.3Kbit/s and 52.3Kbit/s, occupying 18,710ALUTs and 6,380 Memory bits.