The Research And Designs Of Fast Hardware Implementation Algorithm For Elliptic Curve Cryptography

Public-key cipher system can effectively solve problems about digital signature, identification and key distribution in public channel. So it is used in many domains such as secrecy communication, electron business affairs and electron government affair. Elliptic Curvy Cryptography (ECC) gradually displaced the position of RSA in public key cryptology, because of its specific advantage in security, operation speed and circuit area etc. This thesis is focused on solving the contradiction of operation speed, flexibility and circuit area in elliptic curvy cryptography designed circuits. It aims to improve efficiency and flexibility of elliptic curvy cryptography processing. Based on the finite field of ECC, it gives the theory of redundant signed digit system. At the same time, it provides a series of arithmetic and hardware design of redundant signed digit system. The research ensures the efficiency and flexibility of different ECC hardware design at the bottom. The hardware design also be taken for the hardcore of ECC coprocessor. The main contribution of this dissertation can be summarized as following:1. The dissertation researches the hardware expressive method of redundant-binary signed digit system. Combining the requirement of ECC finite field operation, it analyzes the Boolean logic of hybrid signed number adder and binary signed number adder basis of the traditional signed number adder.Then corresponding arithmetic units are designed.2. The arithmetic of modular addition/modular subtraction basis of signed digit system is presented. Referring to the incomplete reduction number 's thinking, firstly, the arithmetic of modular add/modular subtraction basis of word is improved to the arithmetic of modular add/modular subtraction basis of the incomplete reduction number. Secondly, in order to reduce the key data path delay of the hardware structure basis of the incomplete reduction number arithmetic of modular add/modular subtraction, the arithmetic of dual-field modular add/modular subtraction basis of signed digit system is presented. Thirdly, the hardware structure of dual-field modular addition/modular subtraction basis of signed digit system is designed. The hardware structure supports not only the arithmetic of dual-field modular add/modular subtraction but also the flexibility of operand's length. So it has some more advantages in operation speed and circuit area.3. We describe the arithmetic of Montgomery Multiplication basis of signed digit system. From the point of view which improving operation speed and reducing circuit area, we select the arithmetic of Montgomery Multiplication basis of word, and put forward a sort of effective dual-field Montgomery Multiplication basis of signed digit system. Next, we describe the Montgomery Algorithm and it's hardware implement.4. We describe the arithmetic of Montgomery Inversion basis of signed digit system. According to the common ground of prime number inversion algorithm and binary inversion algorithm, after deeply researching the original arithmetic of Montgomery Inversion, we put forward a sort of flexible dual-field Montgomery Inversion basis of signed digit system. Next, we design the flexible dual-field Montgomery Inversion algorithm and it's hardware implement.