Design And FPGA-based Implementation Of List-serial SCL Decoder For Polar Codes

Polar codes are widely seen as a major breakthrough in coding theory.They are the first error-correcting codes with an explicit construction to provably achieve channel capacity.The successive cancellation list(SCL)decoding algorithm can effectively suppress the error propagation phenomenon in the successive cancellation(SC)decoding algorithm,which can improve the error correction performance under the medium and short codes.It is one of the most widely used decoding algorithms of polar codes at present.The existing hardware implementation of SCL decoders mostly use list-parallel structure,in which calculation modules need to wait for each other for a considerable length of time.As a result,these decoders have a large amount of idle time and low resource utilization.In order to solve the above problems,this thesis designs a list-serial SCL decoder for polar codes.With consistent error correction performance,this decoder can improve throughput,resource consumption and resource utilization efficiency.Firstly,this thesis introduces the basic theory of polar codes,the SC and the SCL decoding algorithm,and relevant examples are given.The implementation structure of SC decoder for polar codes is described.The working sequence of the existing SCL decoders is analyzed,which shows that these decoders have low resource utilization efficiency.In order to improve the resource utilization of the hardware implementation of SCL decoders,a list-serial SCL decoder for polar codes is designed in this thesis.Serial pipeline calculation is used between paths to reduce the waiting time between inner modules.In single path calculation,a semi-parallel structure with multiple processing units is adopted to reduce the excessive delay caused by serial calculation.The algorithm is simulated in MATLAB,and results show that the list-serial SCL decoder can achieve the same error correction performance as the list-parallel structure decoder.Finally,the list-serial SCL decoder is implemented on the Field Programmable Gate Array(FPGA),and its correctness is verified by MATLAB and FPGA co-simulation system.Compared with the list-parallel decoder,the throughput of the list-serial SCL decoder can be increased by 59%,the consumption of look-up table(LUT)is reduced by 51%,and the resource utilization efficiency is significantly improved.In summary,in order to solve the problem of low resource utilization of the existing list-parallel SCL decoders,this thesis designs a list-serial SCL decoder and implements it on FPGA.The simulation and test results show that it can greatly improve the throughput,and reduces resource consumption while maintaining consistent error correction performance.