Research On Low Latency Polar Code Decoding Algorithm And VLSI Design

With the continuous innovation of mobile communication technology,the fifth generation mobile communication(5G)is coming.ITU divides 5G into three application scenarios: enhanced mobile broadband(enhanced Mobile Broadband,eMBB),large-scale machine communication(massive Machine Type Communications,mMTC),high reliability and low delaycommunication(Ultra-Reliable and Low Latency Communications,uRLLC).Polar Code is a control channel coding scheme in 5G network eMBB scenario by virtue of its advantage of reaching “Shannon limit”in theory.In order to meet the needs of large-scale wireless communication,the real-time performance of the receiver decoding algorithm is particularly important,especially in finding an excellent decoding algorithm to improve the performance of the polarization decoding system.This paper will focus on studying polar codes decoding algorithm,optimizing the serial cancellation decoding algorithm and the serial cancellation list decoding algorithm,and completing the hardware circuit design.The main contribution is as follows:1.A Successive Cancellation decoding algorithm based on partial decoding modeSuccessive Cancellation(SC)decoding algorithm,as the first proposed decoding algorithm in polar code decoder,has been widely studied.However,the existing architecture for large-scale communication systems has drawbacks such as high hardware complexity and long processing delay.In this paper,the conventional SC decoding algorithm is studied and the hardware circuit optimization design of the algorithm is completed.Firstly,based on the Binary Eliminated Channel(BEC)channel,the reliability of the polarized channel is evaluated by the Bhattacharyya Parameter method.The polar code bits are divided into frozen bits and information bits,where the frozen bits are known bits.By removing the decoding of paired fixed bits of adjacent channels,the conventional decoding algorithm is changed from bit-by-bit serial decoding into pairwise partial decoding(Partial Successive Cancellation,PSC),simplifying the formula of logarithmic likelihood ratio and reducing the complexity of hardware design.The simulation results show that when the code length is N,the decoding period of PSC decoding algorithm decreases from 2N-2 to N-3~7N/8,and the throughput of the decoder increases by 1~8/7 times compared with that before optimization.2.A Successive Cancellation List decoding algorithm based on Log-Likelihood ratio pre-judgment mechanismThe successive cancellation list(SCL)decoding algorithm solves the problem of error transmission in the successive cancellation(SC),but increases the complexity of path splitting and filtering,resulting in large delay.Therefore,how to reduce the splitting of the decoding path has become one key issue in this paper.This paper proposes a pre-judgment mechanism based on log-likelihood ratio symbol,reducing redundant split for SCL(RRS-SCL).According to the log-likelihood ratio symbol decision of each layer,it is split into path "1" or path "0" and the fixed bit layer are directly split into known bits,which aims to reduce path splitting and optimize path metric calculation.Based on the scheme,we design RRS-SCL VLSI architecture with N=1024,the code rate R=0.5,and the list width L=2,4,8.The simulation results show that delay is reduced by about 51%,49%,and 46%,respectively.