Study And Design Of Analog To Digital Converter Based On Metal Oxide TFT

Metal-Oxide Thin-Film Transistor(MO TFT)presents advantages of high-mobility,highON/OFF current ration,large-subthreshold regime swing and good-uniformity.Besides,MO TFT can be integrated on flexible and transparent substrate.These merits make MO TFT find its applications in large area electronical system,such as panel display,RFID tag and sensor array.Analog-to-digital converter(ADC)is one of the most important components in a sensor system.ADC converts the analog signal generated by the sensor to digital codes that can be recognized and processed by CPU.In the traditional sensor system,the sampling and amplification of analog signal is accomplished by TFT while the analog to digital conversion is accomplished by an independent ADC chip.On the other hand,integrating ADC by TFT process is more attractive.As it raises integration,reduces interconnection interference and enables the sensor system to be fully transparent and flexible.The main works of this paper are recognized as follows:1.Several new analog circuits have been proposed,containing operational amplifier,comparator and ring oscillator.The design of Digital circuits based on Pseudo-CMOS Structure was also described.For operational amplifier circuit,the optimization for the amplifier based on load-enhancement topology was first discussed.Subsequently,a high-gain single-stage amplifier based on a modified transconductance-enhancement topology has been proposed.This amplifier shows an DC voltage gain as 46 d B with a gain-bandwidth-product(GBP)as800 k Hz under the measurement setup.After that,the design of multi-stage operational amplifier using feedthrough compensation(FFC)was studied.Two kinds of 2-stage amplifier using FFC have been proposed and fabricated.These amplifiers show DC voltage gain as 60 d B and 40 d B,respectively.And they present GBP as 400 k Hz and 710 k Hz,respectively.For comparator circuit,two kinds of latch comparator based on Pseudo-CMOS structure and bootstrap structure are proposed,respectively.Subsequently a 3-stage comparator constructed by a 2-stage preamplifier and the Pseudo-CMOS based latch stage was proposed and fabricated.The maximum clock frequency of the 3-stage comparator is 100 k Hz and the minimum resolution of the 3-stage comparator is 30 m V.For ring oscillator circuit,a new ring oscillator combining the bootstrap inverter and the skewed delay scheme was proposed.The design of adaptive output buffer was also described.When the supply voltage ranges from 6 V to 20 V,the oscillation frequency of the new oscillator is measured to be at least 45% higher and the power-delay-product is measured to be at least 30% lower than that of the conventional oscillator.Besides,the adaptive output buffer and the conventional buffer have been independently fabricated and measured.The new output buffer presents higher output swing under the same load condition.2.A 1-bit first order ?? ADC and a 3-bit SAR ADC have been proposed and fabricated.The ADC make use of the 60 d B 2-stage operational amplifier and the 3-stage comparator mentioned above.The measurement result shows that the ?? ADC can work under the sampling frequency of 20 k Hz.The peak SNDR is 65 d B over a bandwidth as 30 Hz or 42 d B over a bandwidth as 303 Hz.The 3-bit SAR ADC can work under the sampling frequency of 20 k Hz.The maximum measured DNL and INL is 0.21 LSB and 0.29 LSB,respectively.The peak SNDR over the bandwidth of 10 k Hz is 16.8 d B.