Research And Design Of Floating-point Processor Supporting Dynamic Reconfiguration Of Data Path

In high-density computing fields such as graphics and images,scientific computing,and big data analysis,traditional general-purpose processors and application-specific integrated circuits cannot meet the dual requirements of high performance and high flexibility.The reconfigurable processor combines the functional flexibility of the instruction stream-driven processor and the high energy efficiency of the data streamdriven processor,so it has received extensive attention in the field of high-density computing.The coarse-grained reconfigurable processor is driven by data flow and based on task scheduling to reconfigure the calculation process of the array,which is suitable for performing calculation tasks without control branches and addressing mode rules.The heterogeneous multi-core system of the research group faces the field of high-density computing,and its integrated general-purpose floating-point processor needs to meet the dual requirements of high performance and applicability.In response to the acceleration requirements of irregular addressing mode tasks in high-performance computing,this dissertation designs a floating-point processor that supports dynamic reconfiguration of data paths.The main work and innovations are as follows(1)Different from traditional reconfigurable processors,the design introduces an implementation method based on fusion instructions.(2)Aiming at the characteristics of large hardware scale and big difference in using frequency of floating-point computing components,a direct interconnection network with a smaller network scale than the crossbar switch network is designed.(3)In response to the reconfigurable unit's demand for memory bandwidth,a multiport memory with conflict-free access rules is designed.(4)In the reconfigurable processor,out-of-order execution and out-of-order write-back of multi-pipeline calculation paths are realized.Each memory access channel automatically resolves data conflicts between paths according to the priority of each memory access channel.(5)A compiler suitable for reconfigurable floating-point processors is designed,which makes it possible to map complex applications on this processor.At the end of the dissertation,multiple complex computing tasks are mapped to the reconfigurable floating-point processor.Compared with the general-purpose processor,the dissertation proves the high performance of the floating-point processor.Compared with other floating-point processors,the dissertation proves that this floating-point processor has high performance and can adapt to irregular operations better than the existing work.The target application system integrates 24 reconfigurable floating-point processors,which have been prototyped and verified on the Xilinx Ultrascale series FPGA chip named xcvu440,and the system can work stably at a frequency of 76 MHz.Compared with the previous generation system,the multi-core system with integrated reconfigurable floating-point processor improves the system performance by nearly 2times when executing radar imaging algorithms.