The Research And Application Of Gate Level Near-threshold Energy-efficient Matched Filter Optimization

Since the beginning of the 21st century,the developments and implementations of wearable electronic devices continue to flourish,and low power GPS Chip has been widely used among these devices.GPS Chip can get sub-second responsiveness with the assistance of matched filter.The major problem of matched filter is the complexity of hardware implementation which can lead to a huge runtime power consumption.Some analysts have pointed out that the matched filter consumes more than 55%of the total power of GPS baseband.Thus,optimization of matched filter power consumption is important for reducing the overall power consumption of GPS Chip.The matched filter consists of two parts:calculation module and shift module.Different measures should be taken for each part.For calculation module,the 14-bit operand can be divided into 2 parts,the lowest 4-bit and the highest 10-bit.For the lowest bits,an approximate adder of LSB=2 is involved.This kind of adder can help reduce 36%of the total amount of adders,while it would not affect the SNR of matched filter.For the highest bits,this dissertation gives out an analytic model for layout optimization of adder.This optimal adder shows an 25%improvement on energy efficiency.For shift module,a dynamic flip-flop called C2MOS is used.It could provide a 30%reduction of power compared to traditional flip-flop.A yield optimization method is also proposed to overcome the process variation in near-threshold region.The physical implementation is executed under SMIC40,0.6V.With all of the optimization above,a power reduction of 47%has achieved.This matched filter has an advantage of energy efficiency when compared to other matched filter design,and it shows an increment of 33%in TOPS/mW,from 0.0617 TOPS/mW to 0.0819 TOPS/mW.