Design of robust energy-efficient digital circuits using geometric programming

Power dissipation has become a critical design constraint in all digital systems. Designers must focus on creating energy-efficient circuits to achieve the highest performance within a specified energy budget or dissipate the lowest energy for a given performance. In addition, as technology scales, increasing process variations can significantly degrade circuit timing and power. These variations must be accounted for during design to produce robust circuits that guarantee a desired performance after fabrication.; This thesis focuses on the automated design of robust energy-efficient digital circuits. Using device sizes and supply and threshold voltages as variables, we formulate the energy-efficient circuit design problem as a Geometric Program. GPs are a special class of convex optimization problems and can be solved efficiently. We develop analytical models of gate delay and energy, and include different design scenarios like changing logic styles, discrete threshold voltages, wire resistances and capacitances, signal slope constraints and so on in the optimization. To facilitate design entry and post-optimization analysis, we have built the Stanford Circuit Optimization Tool (SCOT). As a design case study we explore the energy-delay tradeoff of different 32bit adder topologies using SCOT. These tradeoff curves show that adders with an average fanin of two per stage having the fewest logic stages and smallest wire overhead are most energy-efficient.; Gate delay uncertainties due to process variations cause a spread in the overall circuit delay. We show how deterministic sizing, which optimizes the nominal delay ignoring process variations, can make the overall delay much worse under variations because it results into many critical paths that may contain small devices.; To solve this problem, we propose two heuristics that guide the optimizer to create a solution that comes close to optimizing the performance that guarantees a desired yield. First, we augment the gate delay models with standard deviation delay margins. Second, we use a "soft max" function to combine path delays at converging nodes. Using these heuristics retains the original GP form of deterministic sizing and therefore incurs only a modest computational overhead. The improvement in robustness over deterministic sizing depends on the circuit topology and the extent of variations specified by the technology. For a 90nm technology, assuming a 15% standard deviation in the delay of a 1mu wide drive transistor, results show that using the proposed heuristic techniques of statistical sizing with the correct statistical estimate of overall energy improves the energy-delay tradeoff curve by 10% for 32-bit adders.