Research On Near-Threshold Energy-Efficient Processor Design Based On Timing Error Resilience

With the increase of the power density and the diversity of applications,an energy-efficient processor is highly demanded in a system.Near-threshold computing is a promising technique to address the power bottleneck and achieve high energy efficiency,which is bound to become a new development trend of integrated circuits.However,the biggest challenge in designing near-threshold computing hardware is large delay variability.Therefore,variation tolerance is critical to exploit the potential of near-threshold computing.This thesis focuses on timing error-resilient techniques for dynamic variation tolerance.The main contributions of this thesis are described as follows.1.Circuit research of timing error resilience.The previous error-resilient flip-flop circuits suffer from two critical problems:the detection metastability and the correction overhead.To mitigate these two problems,a metastability-immune error-resilient flip-flop is proposed.It detects timing errors by generating a pulse in response to the data input transition and capturing the pulse during the high clock phase.The pulse width is larger than the setup time window to handle the data input transition during the setup window as a timing error.To immediately correct timing errors,it dynamically makes the master latch transparent to resample the late-arriving data.Thus,the late-arriving data is passed to the slave latch by reusing the existing data path.The proposed circuit technique avoids the metastability problem to improve the reliability of timing error-resilient processors at the near-threshold regime,and reduces the correction overhead.2.Instruction set architecture research of timing error resilience.To address the limitations of applicability in the existing error correction schemes,the following two inherent characteristics are extracted from different instruction set architectures,which are independent of implementation details of processors.First,architecture registers are enough for resuming correct execution.Second,each instruction only updates a small proportion of architecture registers.According to these two characteristics,a timing error correction scheme based on instruction-level architecture state tracking is proposed.It uses sacrificial registers to dynamically capture and incrementally record the changes of architecture registers at each instruction boundary.Once a timing error occurs,it only needs to restore the changed architecture registers to a pre-error state by sacrificial registers.Then,the erroneous instruction can be safely re-executed.The proposed architecture technique can be applicable to different processors.3.Filtering framework research of timing error resilience.Through theoretical and statistical analyses,timing error characteristics can be classified into three categories:transient timing error,repeated timing error,and short-path timing error.According to these timing error characteristics,a new timing error-resilient framework based on dynamic multi-level filters is proposed.It uses dynamic multi-level filters for identifying and handling three types of timing errors separately.When a timing error cannot be handled at the current level,it will be filtered into the next level to be identified and handled.This process continues until the timing error is corrected.Therefore,all kinds of timing errors can be optimally processed in different levels.The proposed framework technique decreases the performance penalty of error correction and the hardware overhead of short-path padding.In addition,it is expansible and has low design overheads.Techniques proposed in this thesis facilitate the timing error-resilient system,and establish the theoretical and practical foundation for tolerating variations and improving the energy efficiency of near-threshold processors.