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Design Of LDO With Ultra-low Quiescent Current

Posted on:2022-03-28Degree:MasterType:Thesis
Country:ChinaCandidate:M L HaoFull Text:PDF
GTID:2518306557465634Subject:IC Engineering
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With the development of integrated circuits and the rapid innovation of electronic products,people have higher performance requirements for power management chips.Low-dropout linear regulator(LDO)occupies an important position in the power management chips market with its advantages of low cost,low power consumption,small ripple and simple structure.Currently,the portable electronic products require longer battery life,the battery consumption can be reduced and the battery life can be extended by reducing the quiescent current.This thesis designs an ultra-low quiescent current LDO suitable for portable electronic equipment,after studying the basic theoretical knowledge of LDO.The LDO mainly includereference voltage source,error amplifier,dynamic buffer,pass transistorfeedback stage and current adaptation circuit,etc.In order to achieve ultra-low quiescent current,design a bias circuit that works in the subthreshold regionto provide n A-level current to each module.This paper proposesa depletion-type lowpower reference voltage sourceto provide a reference voltage for the error amplifier.Let the error amplifier operate in the sub-threshold region to further reduce the quiescent current.Adds a dynamic buffer to enhance the control voltage slew rate and improves the transient characteristics.At the same time,design an adaptive current jump circuit based on the traditional current adaptive technology,which achieves ultra-low quiescent current at no load and good transient response characteristics at load.Introduce a dynamic zero point in the loop to achieve tracking compensation to ensure loop stability in the full load range.In addition,this article also design some auxiliary circuits to protect the chip,such as current limiting protection and temperature protection,etc.Based on the CSMC 0.5?m CMOS process,the LDO circuit is been verified to meet the design specifications by Cadence software simulation,and complete the overall layout drawing work.The test results show that: it can output 1.8V stably within the input voltage range of 2.5?5V.Its maximum load is 300 m A,and the overshoot voltage is less than 60 m V when the load changes in the range of50 m A.It can work normally in the temperature range of-40?85?.The quiescent current is as low as 380 n A at no load,realize the design index of ultra-low quiescent current.
Keywords/Search Tags:low dropout linear regulator(LDO), low quiescent current, depletion reference, current adaptation technology, low power consumption
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