Design And Optimization Of New Structures For MOSFET Power Devices

MOSFET power devices have the advantages of large safe working area,easy parallel connection,fast switching speed and low driving power,which are widely used in industrial manufacturing,high voltage transmission,household appliances and aerospace.However,there is a paradoxical relationship between the breakdown voltage and the specific on-resistance of MOSFET power devices of order 2.5.When the breakdown voltage increases,the on-resistance increases significantly,leading to a decrease in device performance.This paper revolves around how to increase the breakdown voltage of the device while improving the on-state characteristics.Three new structures for MOSFET power devices are proposed:（1）A low on-resistance,high-voltage SOI LDMOS structure with multiple P-buried layers,which consists of a step-doped drift region and multiple P-buried layers with decreasing length and concentration in the vertical direction.Using multiple P-buried layers,the doping concentration in the drift region can be increased,thereby reducing its specific on-resistance and modulating the internal electric field of the device to increase its breakdown voltage.In addition the drift region concentration is distributed by step doping,which can accommodate more impurity atoms and provide more electrons to support higher currents,thus reducing its on-resistance and generating a new electric field peak on the device surface,which further increases its breakdown voltage.The simulation results show that the PL-SOI LDMOS has a specific on-resistance of 15.8 mΩ·cm²and a breakdown voltage of 281 V.Compared with the conventional SOI LDMOS,the specific on-resistance is reduced by 35.8%and the breakdown voltage is increased by 55.2%.（2）A VDMOS structure with enhanced current capability using electron-hole conduction,which consists of NMOS and PMOS.The gate voltage(V_GP)of PMOS is introduced from inside the drift region of NMOS,and the electron current passes through the equivalent resistance R between the lead gate and drain in the N drift region,resulting in a voltage drop V_GPD that determines PMOS switching.The proposed PN-VDMOS uses simultaneous electron-hole conduction to significantly increase the current capability,and the simulation results show that the saturation conduction current of PN-VDMOS is 7.8×10^-5 A.Compared to conventional VDMOS,the saturation on-state current is increased by330%and the breakdown voltage is increased from 455 V to 514 V.（3）A current-enhancing stacked MOS structure that consists of LDMOS1 and LDMOS2 stacked together,using a U-shaped gate to control LDMOS1 and LDMOS2.Since this structure has two current paths,its on-state current boost is large.The introduction of the P-top region inside the device improves the drain field distribution and increases the concentration of the LDMOS1 drift region,thereby improving the device breakdown voltage and specific on-resistance.The simulation results show that the saturation on-current of the stacked LDMOS device is 1.11×10^-4 A,the breakdown voltage is 339 V,and the specific on-resistance is 15.8 mΩ·cm².Compared with the conventional LDMOS structure,the saturation on-current is 196%higher,the breakdown voltage is 31%higher,and the specific on-resistance is 42%lower.