Design And Implementation Of High-Speed On-Board Router Switch Unit

With the rapid development of communication technology,information globalization has become an urgent need for human development all over the world.Due to the limitations of ground communication equipments,the flexible and reliable satellite communication network with a wide coverage area and the independent of geographical influences,which has been widely used in many fields,has become an important part of the current integrated space information network.With the continuous advancement of on-board integrated circuit technology,the low-orbit satellite network formed by multiple LEO satellites uses the routing transmission mechanism of inter-satellite links to realize the interconnection and intercommunication between satellites.It can form a satellite Internet with the terrestrial Internet to support broadband access services for a variety of streaming media services and conform to the current development trend of 5G mobile communications.However,the explosive growth of network data traffic and the increasing availability of access services have made the system bandwidth and service quality of satellite Internet facing higher requirements.In addition,the dynamically changing network topology of loworbit satellites and the limited storage and computing resources on board also make the routing and transmission of inter-satellite links face severe challenges.As the core of the low-orbit satellite network node,the on-board routing and switching equipments have a direct impact on the delay and throughput of the entire satellite network.Based on the "Design and Implementation of High-Speed On-board Router" project undertaken by the laboratory,this thesis focuses on the design and implementation of high-performance queue management technology and queue scheduling technology for the on-board switching.This thesis first introduces the research background and development trend of low-orbit satellite Internet.Secondly,by analyzing the project requirements,a design scheme for the high-speed on-board router based on shared memory has been put forward,focusing on the specific implementation of the data switching plane.Third,the overall architecture of the queue management and bus control scheme with high-speed pipeline performance has been designed and realized,focusing on the functions,interactive interfaces and detailed design schemes of some key sub-modules such as enqueue and dequeue.Fourth,by analyzing typical queue scheduling algorithms,we design and implement a multi-level queue scheduling scheme for ports and priority queues.Finally,the simulation software has been used to perform functional simulation tests on the completed key modules,and board-level test verification has been carried out on the actual relevant switch board,which prove that the designed queue management scheme and queue scheduling scheme are reasonable in design,stable in performance,and able to meet the design requirements of the project.We propose three innovations in this thesis.First of all,The original queue management scheme has been divided into in-depth pipelines,and we propose a queue management scheme with high-speed pipeline performance,which further improves the processing speed and efficiency of the data exchange plane.Second,The RR polling algorithm has been combined with the port feedback mechanism to strengthen the accuracy and reliability of the queue scheduling results.The strict priority mechanism has been used in the DWRR polling algorithm,so that the DWRR algorithm can well support delay-sensitive transmission services;Third,we design and implement a multi-level queue scheduling scheme using a compound scheduling algorithm.By introducing a token bucket mechanism,we have realized specific functions such as flow control,multi-level scheduling,and bandwidth borrowing.