Research On Single Event Effect Of SiC MOSFET And Its Method Of Resisting Single Event Effect

SiC MOSFET has become an indispensable device in the power circuit of aerospace systems due to its high temperature resistance,low loss,fast switching speed and high blocking voltage.However,in recent years,due to the increasing integration and complexity of aerospace systems,power semiconductor devices have also become smaller,more integrated,and more systematic.Therefore,the single-event effect of the power device SiC MOSFET working in the radiation environment is becoming more and more serious,and will gradually become one of the main reasons for the failure of the radiation effect of space electronic equipment.The failure of SiC MOSFET may cause the power system of the aerospace system to be unstable,affecting the safety of the aerospace system in orbit.Therefore,it is very important to improve the ability of the SiC MOSFET device to resist single event effects.In this paper,the single event effect of SiC MOSFET was studied based on the simulation technology.First,the cell structure of SiC MOSFET is constructed,then the failure mechanism of single-event burnout(SEB)and single-event gate rapture(SEGR)of SiC MOSFET is studied.The effects of particle linear energy transfer(LET),incident position,incident angle,and drain-source voltage on SEB of SiC MOSFET devices are also discussed.The effects of particle incident point and LET on SEGR of SiC MOSFET devices are also analyzed.The results show that the occurrence of SEB in the SiC MOSFET is related to the state of the parasitic bipolar transistor inside the device,and the occurrence of SEGR in the device SiC MOSFET is related to the transient electric field formed under the gate dielectric layer of the device;The risk of SEB and SEGR is the highest when particles enter the SiC MOSFET device perpendicularly from the middle of the gate.As the LET of the particles and the drain-source voltage of the device increase,SiC MOSFET devices are more likely to produce SEB and SEGR.In this paper,adding a buffer layer with a suitable concentration can improve the SEB resistance of the SiC MOSFET,and use of high dielectric constant materials as the gate dielectric layer can improve the SEGR resistance of the device.The hardened structure combination of the two methods can improve the SEB resistance of the device and reduce the risk of SEGR of SiC MOSFET.This research may contribute to the SEB and SEGR hardened structure design of SiC MOSFET.