Research On Novel Vertical MOSFET And Its Extended Structure

In recent decades,the feature length of transistors has been gradually reduced in accordance with Moore's Law.After reaching the nanometer scale,the serious shortchannel effect has greatly hindered the further improvement of device performance.In this context,FinFET and GAAFET have been proposed one after another.Because of their innovations in transistor structure,they have superior performance advantages compared to traditional planar MOS.However,FinFET and GAAFET are not perfect devices.Their channels usually use lightly doped or even undoped intrinsic silicon to reduce scattering.The tri-gate or quad-gate structure is used to strengthen the gate's control over the channel.There are a series of problems such as low Breakdown voltage and difficulty in adjusting W/L.Our team proposed a novel vertical MOSFET structure to solve the shortcomings of FinFET and GAAFET.The channel region of the novel vertical MOSFET is heavily doped,and lightly doped drift regions are added between the drain and the channel and between the source and the channel.Due to the vertical structure,the drift region structure will improve the the Breakdown voltage and not occupy the chip area.At the same time,the novel vertical MOSFET can easily adjust the channel width by adjusting the number of conductive channel sides,and the channel length can no longer be restricted by the photolithography process,so it is easy to achieve any W/L.Based on this novel vertical MOSFET structure,a novel DRAM cell structure and a novel CMOS inverter cell structure are designed,and analysis and simulation were completed.The specific content is as follows:1.The model construction and electrical characteristics simulation of the novel vertical MOSFET are carried out through Sentaurus software,and the transfer characteristic curve,output characteristic curve,threshold voltage and leakage current of the transistor are obtained.2.Based on the novel vertical MOSFET,a new type of DRAM cell using trench capacitors is designed,and its model construction and function simulation verification are carried out.Then,by analyzing the change trend of the data writing speed and retention time of the DRAM cell under different parameters,the model structure after parameter optimization is obtained and the simulation results are given.Finally,the process realization method of the novel DRAM cell is provided.3.A new type of CMOS inverter unit is designed based on the novel vertical MOSFET,and its model construction and function simulation verification are carried out.By deepening the gate length,the problem that the output level cannot reach the theoretical high and low values is solved.Then through the analysis of the change trend of the spread delay and switching threshold of the CMOS inverter structure under different parameters,the model structure after parameter optimization is obtained and the simulation results are given.The function of optimized model structure is verified by designing abnormal input waveforms,and the output was confirmed to meet theoretical expectations.Finally,the process realization method of the novel CMOS inverter unit is provided.