Design and implementation of longest prefix matching content addressable memory for IP routing

To cope with the growth in the internet and corporate IP networks, IP routers are required to be capable of much higher performance than is possible with existing architectures. A router forwards a packet based on the packet destination address by finding the longest matching prefix in the IP lookup tables. IP lookup has become a major performance bottleneck for the routers. A solution to this problem must simultaneously achieve high lookup rates, good update performance, high memory efficiency, and low hardware cost. Ternary content addressable memories (TCAMs) have emerged as a popular device in designing the matching block for routers. Despite their high-throughput, large TCAM arrays have excessive power consumption and are not easily scalable to large addresses.;This work presents internet protocol content addressable memory (IPCAM) architecture that directly computes the longest prefix match for the incoming IP address. A dynamic implementation and a static implementation are proposed. Both provide about 10x savings in terms of area and power as compared to a state of the art TCAM design. The IPCAM design produces encoded prefix match length information that is limited by a prefix mask, so the entries do not need to be sorted in prefix length order as is required for a TCAM design. The encoded outputs drive a priority encoder to determine the longest prefix match in the IPCAM arrays. Priority encoder circuit architectures appropriate to the unsorted IPCAM entries are also presented. Although targeted for IPv4, the proposed architecture is easily scalable to IPv6.