Design And Implementation Of PCIe Interface And LDPC Decoder Based On Domestic Chips

In order to cope with the current international situation and the domestic information industry's demand for core technology,instruments and equipment in key areas are gradually getting rid of the situation of relying heavily on imports for chips.However,due to the large differences between domestic and foreign core technologies and platform architectures,to promote the application fields of domestic chips,it is imperative to migrate the existing upper-level applications and be compatible with domestic platforms.Under the above background,this subject is based on the Loongson and domestic FPGA platform to complete the PCIe interface logic and LDPC decoder design,providing a case for domestic engineering applications.The main research contents of this thesis are as follows:(1)At first,the PCIe bus topology,hierarchical structure,and the main functions of each layer are briefly described.The TLP structure and PCIe transaction requests are analyzed,and the Type 0 configuration space definition of PCIe devices and the principles of three interrupt mechanisms are given.Then,the characteristics of the four LDPC decoding algorithms and the feasibility of hardware implementation are mainly analyzed,and the iterative steps of the OMS decoding algorithm are studied with the help of Tanner graphs.At last,based on the QC-LDPC code with a code rate of 0.4 and a code length of 155,the decoding performance of MS,OMS and LLR-BP decoding algorithms are compared.Comprehensive calculation complexity and performance,OMS decoding algorithm has high engineering application value.The above theories provide theoretical guidance for system design based on domestic platforms.(2)The DMA controller and LDPC decoder system based on domestic FPGA are designed.Firstly,the system functions and relevant configuration parameters of PCIe IP core are introduced.Secondly,it focuses on the analysis of the the Finite State Machine(FSM)transfer process of the RX,TX engine and interrupt controller in the DMA controller,completing the AXI-TRN protocol conversion and the definition of the control state machine register,and writing test cases based on the RP simulation platform for the DMA controller functional simulation.Finally,the LDPC decoder modules are designed with a serial structure,and the design of the control module,VNU,CNU,and decoding decision module is described in detail.The 'FIFO+BRAM' solution is used to solve the problem of data access and bit width conversion between the DMA controller and the LDPC decoder.The hardware system scheme clarifies the development requirements of the driver and the host computer.(3)Above all,the PCIe driver was developed based on the Loongson operating system,and the PCIe driver framework was studied,and the functions of loading and unloading,initializing and shutting down the driver were realized.The open,read,write,ioctl,and release interface functions are defined in the file operations structure,and the design ideas for the read and write functions and interrupt operations related to the DMA mode are given.In the next place,the upper computer completes the calculation of the initial likelihood value of the channel,and sends the data to be decoded to the PCIe device by calling the API function,and the LDPC decoder completes the decoding.The simulation comparison with the OMS decoding algorithm in Matlab shows that the LDPC decoder has perfect functions and meets expectations.In the end,the results of the PCIe transfer rate test show that the DMA read and write rates can reach 1427 MB/s and 1620 MB/s,respectively,and the maximum bandwidth is 84% of the theoretical bandwidth of the PCIe interface.