Research On Cache And Its Coherence Protocol Based On RISC-V Multi-core Processor

Modern processors generally utilize cache to alleviate the performance gap between the processor and the main memory.However,an increase in the cache capacity is usually accompanied by a decrease in the access speed.In order to satisfy the requirement of approximately the same frequency as the processor core,L1 cache is destined to not be large,which limits the development of high-performance processors.Therefore,it is of great significance to explore the tradeoff between cache capacity and frequency and design a high-frequency large-capacity cache.In addition,with the rapid development of integrated circuit technology,more requirements have been raised to the performance of processors.Multi-core and even many-core processors are becoming an inevitable developing trend,while the resulting memory consistency problem will also become more prominent.Cache coherence protocols are necessary to the correctness of multi-core processors.Research on low-latency and high-efficiency cache coherence protocols is critical for improving the overall performance of multi-core processors.RISC-V is an open source instruction set architecture proposed by the researchers at University of California,Berkeley.Its attractive features,such as free,flexible,and customizable,make RISC-V processors quickly become a hot research topic.Based on the RISC-V multi-core processor,this thesis studies the cache and its coherence protocols,aiming to improve the performance of the processor.The main contents and research results of this thesis can be summarized as follows.1.A high-frequency,low-power,large-capacity instruction cache architecture,D2MB-ICache,is designed based on divide-by-2 memory banks.Aiming to ensure the correct function of the D2MB-ICache and its expansion without frequency reduction,this thesis provides a partition mechanism and an inversed clock for divide-by-2 memory banks,and designs a control module for non-sequential accesses.VCS simulation and DC synthesis results show that,compared with the traditional instruction cache,the D2MB-ICache with the same and double capacities shows a maximum frequency increase by an average of 14.6%and 6.8%,and a performance improvement by an average of 10.3% and 3.8%,respectively.Furthermore,when the capacity is 16 kB,32 kB,64 kB and 128 kB,the power consumption in D2MB-ICache is reduced by 0.5%,16.1%,24.3% and 24.8%,respectively.2.A low-latency and high-efficiency cache coherence protocol,DTBDN,is proposed to optimize the original coherence protocol in the TileLink protocol.This protocol not only defines the memory access operation in cache,but also covers the consistency operation for IO devices.Different from the original protocol,the DTBDN protocol distinguishes private copies from shared copies clearly.In the DTBDN protocol,the shared copies are taken directly from the L2 cache,thereby avoiding the simultaneous issue of multiple remote read responses and reducing the bus occupancy rate and cache miss penalty.The Gem5 simulator is used to evaluate the performance of the DTBDN protocol.Experimental results show that,compared with the MESI and MOESI protocols,the DTBDN protocol improves the performance of RISC-V quad-core processor by 2.4% and 1.6%,and improves the performance of RISC-V 8-core processor by 3.6% and 2.5%,respectively.3.This thesis designs a functional verification platform to verify the memory system of the RISC-V multi-core processor by employing the simulation-based verification method.Firstly,this thesis analyzes the characteristics of the target system under verification,and extractes the function points in the cache coherence protocol and the typical test scenarios for the multi-core processor.The typical test scenarios are mainly used to verify the parallel access operations and boundaries in multi-core processors.Then,based on System Verilog,the test platform for the target memory system is designed.Finally,this thesis adopts a hybrid method of random testing along with directional testing,and designs test programs for the memory system of the RISC-V multi-core processor in assembly language and C language.The final output report shows a 100% functional coverage,thus the verification goal is completed.