Rcsarch And Design Of Cache Coherence For Mu11i-core Processors

The development of the IC design and manufacturing technology make themulti-core processor possible. As a result of the advances in the power consumption andthe speed when compared to the single-core processor, the multi-core processor hasbeen greatly developed in recent years.In the multi-core processor, the access of the multiple cores to the shared data isbound to cause data collisions. The cache coherence protocol is designed to deal thisproblems, which make the cores can access the right data in real time.In this project we propose the hybrid cache coherence protocol that bases on thehierarchical framework after we analysis the two traditional cache coherence protocols.This protocol Combines the two traditional protocols in effective ways. In the firstShared bus architecture layer we use the snoopy protocol. In the second NoCarchitecture layer we use the directory-based protocol,which deal with the problems ofthe bus bandwidth in the shared bus architecture and the problems of the directoryspace in the directory-based protocol shows excellent performance.At the same time the concept of the localized cache coherence are proposed tomake the maintenance of the cache coherence only in several specified cores, whichavoids the unnecessary consumption in the global mode and improves the efficiency ofthe coherence protocol.