Research On Cache Coherence Of Multi-core Microprocessor

With the development of computer technology,the performance requirements of computer are getting higher and higher,the core frequency of computer is getting higher and higher.The technology of IC(integrated circuit)manufacturing and the power consumption of chips,and so on,which makes the method of improving the performance of chips by increasing the core frequency of the CPU encounter a great challenge.In a multi-core processor system,in order to ensure the consistency of copy data in each core,a cache coherence protocol must be used to maintain the consistency of the data.The design of the coherence protocol based on snooping is simple,but the coherence maintenance efficiency is low,and the bus communication volume is large.The coherence protocol based on directory has small communication volume,good scalability,but a large directory storage area.As the number of processor cores increases,snooping and directory coherence protocols face issues such as power consumption,area,latency,and communication volume.This paper focuses on the cache coherence protocol model for multi-core processor.Based on the analysis of the traditional cache coherence protocol,this paper proposes a hybrid coherence protocol that combines bus snooping and directory structure.The coherence protocol adopts a layered structure.The internal core of the node transmits status messages through a sharing bus.The snooping coherence protocol based on MOESI(Modified Owned Exclusive Share Invalid)is used.The nodes adopt an on-chip interconnect structure.A directory structure controller is designed to transmit messages,and the directory coherence protocol is used between nodes.Then this paper introduces the maintenance process of the consistency of the core read and write data,and the consistency maintenance process of the DMA(Direct Memory Access)read and write data in the hybrid coherence protocol.A hybrid coherence protocol model based on the SLICC(Specification Language for Implementing Cache Coherence)script language is built in the GEM5(General Execution-driven Multiprocessor Simulator)simulator,and a Python script file is generated by the compiler,which is connected with the memory components in the Ruby module to form a complete cache coherence protocol model.Finally,the parallel test program Splash2(Stanford Parallel Applications for Shared Memory)was used to simulate the performance of the hybrid coherence protocol in the GEM5 simulator.Simulate the performance gap between listening,directory,and hybrid protocols in FS(Full-System)mode and SE(Syscall Emulation)mode.The results show that the hybrid protocol can improve the hit rate of the cache block and effectively reduce the running time of the test program.Especially when the number of cores is 32,the running time is reduced by 8% on average.Simulation of the hybrid coherence protocol 's cache block hit rate and the running time of program for different numbers of cores.The results show that when the number of cores is 32,the program's cache block hit rate is high and the running time is reduced by up to 8%,but as the number of cores continues to increase,the total missing of the cache block and effective time basically no longer decreases.Comparing the cache block hit rate and performance gap of the hybrid protocol under different directory block and different cache block sizes,the results show that the increase of the directory block and the cache block can improve the hit rate of the cache block of the test program and reduce the running time to a certain extent.But the directory structure is too large and the cache block is large,which makes the cache system more complicated and the area scale is huge,resulting in increased traffic and delay.