Research And Design Of Cache Coherence For Multi-core Processors

Multi-core processor was the integration of multiple computing cores on a single processor, which improved processor computing ability through the parallel computing technology of multi-core processors. Single chip multi-processor architecture (CMP-Chip Multiprocessor) was hot spots in this area. The CMP multi-level Cache storage structure was briefly discussed in this paper, which led to Cache coherence problem, the selection of consistency protocol had a major impact on the performance of the CMP system. The selection of model of the Cache Coherence and methods of its design will have a significant impact of overall design and development of CMP.the background and significance of the subject were firstly introduced in this paper, so was quo of CMP and Cache coherence protocol, the CMP structure, advantages and key issues of design were briefly introduced, while the Cache technology was deeply studied, including the structure of Cache, working principle, technology, replacement strategies, writing strategies and so on. The existing two bus snooping protocols were studied—MESI protocol and Dragon protocol, the advantages and disadvantages of two protocols were analyzed: MESI protocol data can be transferred between private Cache of different, resulting in an increase of access time; Dragon protocol, when updated the data in the private Cache of the local processor, updated other Caches which contained the data copy the same time, it extended access time and also took up a lot of bus bandwidth. After studying the shortcomings of the existing protocols, this paper presented a kind of bus snooping protocol called CSC (Coherence with SC-Cache) containing SC-Cache (Shared Coherence Cache) based on write-invalidate and write-back strategy. It was different from traditional protocol that the shared copy of the Cache block exists only in SC-Cache. Each processor accessed SC-Cache to read and write shared block.Finally, the verification process of design and experimental tools were discussed, the results of experimental verification were listed. The protocol was implemented by modifying the code of SimOS system simulator, while the MESI protocol and Dragon protocol was implemented, run SPEC95 in the modified platform respectively, the dynamic experiment results of the processor implementation were recorded. Meanwhile, the data obtained of three protocols to summary of the findings were analyzed, which proved that the CSC protocol reduced delays, improved the accessing speed, and the design elements presented in this paper had a good research value.