A Design For Readout Circuit Of Organic Photodetector

Most of the existing research work of organic photodetector focuses on its material and structure,but the signal readout of organic photodetector is not mentioned too much.Therefore,it is necessary to design a signal readout circuit based on the organic photodetector to meet the test requirements of the project and complete the performance evaluation of the device.The main research content of this paper is about the organic photodetector readout circuit,based on the traditional PCB and separation components to do the relevant demonstration and design work,proposed a low-cost small array readout circuit based on FPGA and board level technology,the main work is as follows:Firstly,the research progress in organic optoelectronic devices by domestic and foreign research teams is analyzed and summarized,and the purpose and significance of this paper are expounded.In terms of overall structure design,referring to the existing research work,the commonly used readout circuit structure is introduced,and after careful argumentation and analysis,various readout circuit structures are compared,and the CTIA readout circuit is taken as the core structure designed in this paper.After completing the selection of the core structure of the readout circuit,not only the basic principles of the CTIA structure are qualitatively analyzed,but also some key performance parameters are quantitatively calculated,and the corresponding calculation formulas are deduced.Secondly,the relationship between performance parameters is analyzed.Then,the design requirements of the readout circuit in the thesis and the overall structure of the system are determined.Finally,a capacitor switching scheme that maintains a linear voltage output during CTIA circuit operation is proposed.Hardware design,based on the PCB process and discrete components design.Some platforms and software tools used in PCB design are introduced,including design software Altium Designer and simulation software Multisim.The hardware design of single channel readout circuit is carried out,including the selection and demonstration of detector unit devices,the structure optimization of readout circuit,and the characteristics of the chip used in it are introduced.The hardware of small array readout circuit is designed.The basic structure is the same as that of the single channel readout circuit,but the single channel is extended to 16 channels.Based on the EP4CE10E22C8 chip of Altera,a FPGA minimum system is designed to control the signal readout of the readout circuit,and also provide hardware support for the subsequent algorithm and program verification.In terms of logic circuit design,the development board used in FPGA logic circuit design,the black gold AX301 and Wildfire minimum core board,as well as the HDL design software Quartus Prime and Model Sim are introduced.The design of clock module is described in detail,including specific clock generation and function simulation results.The logic circuit of the whole readout circuit is also designed,including the generation of the detector gating control signal APD?SW?CTR,and the generation of other readout circuit control signals.At the same time,the function simulation is carried out.The Veriloghdl driver of DAC chip AD5665 RBRUZ is designed.Finally,in the process of completing the above work,the clock signal and timing control signal were tested;the parasitic capacitance and equivalent resistance of silicon-based devices and organic devices were tested;the bias voltage performance of the readout circuit was evaluated;the integral signal and sampling were tested The linearity of the signal;the influence of the integral capacitor size on the integral signal is explored;the influence of the bias voltage on the signal-to-noise ratio of the integral signal is explored.