The System-Level Verification Of Mixed-Signal Based On Verification IP

With the continuous development of information technology,the market has higher and higher requirements for So C(System on Chip)chips,not only requiring the integration of more complex mixed-signal modules in So C chips,but also requiring further improvement of product development efficiency and further reduction of development costs.Mixed-signal verification is becoming more and more important for So C product development,and system-level verification is called a comprehensive physical examination of chip design.Errors found in system-level verification and timely modification of the RTL(Register Transfer Level)design code can effectively reduce the waste of development time and labor costs caused by design errors,and avoid secondary tapeout of the chip.However,the scale of mixed-signal system chips is getting bigger and bigger,and the functions are becoming more and more complicated,which leads to unprecedented challenges in the verification of mixed-signal systems.The main challenges of current mixed-signal verification are that the speed of verification tools is not fast enough,the transistor-level simulation speed is slow,the lack of verification IP(Verification Intellectual Property,VIP)dedicated to mixed-signal design,software and hardware coverification,low-power verification are more complicated,and behavioral-level modeling is time-consuming and labor-intensive.and many more.The research work in this article is based on the development of a certain microcontroller of NXP,and the OPAMP(Operational Amplifier)module in this chip is used as a verification example.The module has both an analog circuit part and a digital circuit part.Through the analysis of the advantages and disadvantages of the existing mixed-signal verification scheme,the module was verified at the system level by adopting the mixed simulation mode.Combining the actual functions of the module,a verification IP dedicated to the module is designed.The excitation generator and waveform checker help to improve the automation of the verification.On the other hand,this research uses a software and hardware co-verification interface IP dedicated to microcontroller verification.This technology can increase the code reuse rate and make code migration between similar modules more convenient.This research is based on the OPAMP module verification IP and software and hardware co-verification interface,combined with the features of the OPAMP module to design a total of 16 verification cases,the module's register read and write function,internal gain mode,follower mode,two power consumption modes,the configuration information rotation configuration mechanism and other functions have been verified.The verification tool used in the verification work is Cadence's efficient and easy-to-use chip development platform IES(Incisive Enterprise Simulator).In the fifth chapter of the article,the procedures of the 6 verification cases are introduced in detail,and the verification results are analyzed.In the end,the test results of all verification cases met the design requirements.This research has improved the efficiency of mixed-signal system-level verification from three aspects: verification tools,dedicated verification IP,and software and hardware co-verification.Compared with traditional verification methods,the verification time of the chip development is reduced to 2 Months,finally the chip was successfully taped out and introduced to the market.