A Research And Implementation On FPGA Virtualization Hardware Framework

Information technology has been widely used in all aspects of life.With new applications emerging,the demand for computing power is also increasing.Cloud computing that uses massive processors to provide computing power for multiple users and heterogeneous computing that uses different architecture computing units are considered to be important solutions to solve the computing power bottleneck and improve resource utilization.FPGA,as programmable circuit device,is one of the core components for constructing heterogeneous computing systems.But due to poor isolation and user-exclusive characteristics,it is incompatible with the current virtualization framework and difficult to integrate into the cloud computing system.As a subproject of the general heterogeneous computing platform,this article aims to develop a multi-user,tailorable,and extensible virtualized hardware architecture suitable for FPGAs.The main content of the thesis is as follows:First of all,the thesis briefly introduces the application scenarios,hardware platforms and its requirements.According to the demand,the dynamic reconfigurable,inter-chip reliable transmission,and intra-chip interconnection bus used in the FPGA virtual hardware architecture are discussed.At the end of this section,the virtualization scheme of the hardware architecture is proposed.Secondly,the RoCEv2 protocol used in the architecture is implemented to provide a low-latency and reliable data path between FPGA-FPGA and FPGA-CPU.This thesis first developed a behavioral simulation model of the RoCEv2 protocol stack based on the OMNe T++ simulation environment to provide guidance for the implementation of the protocol stack.In the implementation stage,the RoCEv2 protocol stack was tailored and a new transmission layer processing pipeline was designed based on the low latency requirements in the target scenarios and the characteristics of short data packets intensive,which greatly improved the data throughput beyond the original design.Finally,a dynamic reconfigurable technology development and operation program on Xilinx devices was proposed,and the deployment was completed on the ZYNQ chip.The thesis summarizes the dynamic reconfigurable engineering development process in the Vivado environment based on the actual engineering,and proposes a feasible layout plan according to the requirements and device characteristics.Subsequently,a data path scheme for reconfigurable modules is proposed,and the communication process and key components are introduced in this thesis.Compared with the existing framework,the virtualized hardware architecture designed in this thesis adds features,such as a unified reliable transmission link for FPGA and CPU and dynamic merging of reconfigurable modules,which enhances the reliability and flexibility of the FPGA system.This thesis provides a foundation for subsequent research on general heterogeneous computing platforms.