Study On The Structure And Characteristics Of A Novel Vertical CMOS Device

With the rapid development of integrated circuits,the key dimensions of silicon-based CMOS technology have become extremely small."Moore's Law",regarded as the golden rule by the industry,is facing failure.The development of the chip follows the development of the application.In the"post-Moore era,"chip update iterations are getting slower and slower.It is no longer possible to improve integration by simply reducing the size.While silicon can't be completely replaced by other materials,we have to find other ways to further improve chip performance.Difficult process and high cost are the main reasons why some high-performance chips are difficult to mass produce.To solve the above problems,it is proposed that a basic integrated circuit unit of vertical structure with excellent performance,high feasibility and simple process.The details are as follows:The article firstly introduced some conventional CMOS technologies,including the structure of the traditional planar metal-oxide-semiconductor field-effect transistor and the three-dimensional Fin FET and GAAFET,and some special processes about them.Then the transistors with longitudinal structure are introduced,and their advantages and disadvantages are analyzed.Thus,the core structure of this paper,a new CMOS basic unit with vertical structure,is introduced.The structure is based on conventional crystalline silicon.The source can be made of various materials,such as silicon,germanium and silicon germanium.Its structural features are as follows:(1)The source is in the center,surrounded by the gate,and the multi-faceted channel conducts electricity;(2)The vertical structure of the N-type device from top to bottom is:N+layer source—P layer channel—N-buffer—N+drain,or N+layer source—N-buffer—P layer channel—N-buffer-N+drain two structures;While P-type devices have exactly opposite impurity types;(3)It is possible for a single device to conduct electricity,or for multiple devices to share a gate or a common source.Next,a detailed process design is given based on the device structure of micron scale process.It is mainly considered from the feasibility of the process and manufacturing cost.In addition to a simple process design,an improved source region self-aligned process is also proposed,in order to decrease the planar area of a single MOS basic unit,thereby increasing the degree of integration.After that,the device structures were modeled in two and three dimensions using the Sentaurus simulation tool.And a series of electrical characteristics including DC and frequency analysis are simulated.When the channel length is 7nm,the threshold voltage of the device is about 0.43V,the switching ratio is in the range of 10~5?10~6,the subthreshold swing is 73.63 m V/dec,and the cutoff frequency is about 5.5THz.These electrical simulation characteristics are much better than known high-performance field effect transistors of the same size.At the end of the paper,a tape-out layout design of the device is given.The mask pattern of six times lithography process is designed by using L-edit tool.The layout consists of six different planar patterns of transistors.Finally,the application prospects of the proposed new vertical CMOS basic unit are analyzed.Due to its excellent electrical properties,the structure is suitable for applications in ideal switches,dynamic random-access memory and radio frequency chips.