Research And Design Of Time Domain Test Scheme For PCI-E Protocol Signal

With the increasing demand of electronic devices for high-speed data transmission,various high-performance serial buses have been developed and advanced.The tests for the widely used PCI-E high-speed protocol bus and interface are also gradually unified and standardized.The test of PCI-E includes two parts: upper protocol test and signal quality test.This paper studies the test probe used in PCI-E upper-level protocol testing and the test fixture used in PCI-E signal quality testing from the technical implementation principle,and designs and implements a protocol signal testing device based on FPGA that can carry out PCI-E signal quality testing,which can generate and send data stream conforming to PCI-E2.0 protocol specification.The main work of this paper is as follows:1.Analyzes the protocol test probe and the working principle of the signal quality test fixture for relay test probe used signal equalization technology,principle of the receiver detection and monitoring type test probe impedance transformation function and the design difficulty of the circuit are studied,and combined with PCI-E LTSSM bottom,fixture design,implementation principle of the test are discussed in this paper,The whole scheme of PCI-E protocol signal test device using FPGA is analyzed.2.The PCI-E data stream generation and transmission part is completed in FPGA,which consists of PCI-E protocol data generation module,CRC verification algorithm module,packet assembly module,clock configuration module,GTX transceiver,etc.,and the 16 bit parallel scrambler algorithm is designed theoretically.The code logic design of PRBS7 generation module and bit error rate detection module is completed.The schematic diagram and high-speed PCB design of the signal conditioning and signal quality verification part in the whole scheme are completed,which is composed of digital signal conditioning module,power module,SMA test interface and signal loop circuit.3.The actual test and analysis of this scheme finally meet the expected performance indicators: serial transmission rate of 5Gbps,data encoding mode of 8B / 10 B,number of channels available 4,output differential signal single-terminal peak-peak between50?600m V,rise time of less than 70 ps,common mode voltage <150m V,total jitter of output signal<77ps,deterministic jitter<57ps,through the design control output impedance 50?.In the end,the case can send five kinds of tlp,3 types of DLLP and the pci-e packet type of PLP in all key information fields in the pci-e protocol specification...