Analysis Of Thermo-mechanical Stress In3-D Package With Through-Silicon Via

With the arrival of the era after Moore’s law,3D packagingtechnology is the inevitable trend in the future and through Silicon via(TSV) is the latest technology of3D packaging which can realize theinterconnection by making through-silicon vias between chips and wafers.The thermal stress caused by the mismatch of coefficient of thermalexpansion between varieties of materials will affect the chip performanceand reliability, which is the problem that must be solved. Therefore, theresearch on thermal stress becomes an important part of the reliability testin3D package.This paper aims at studying the effects of TSVs on chip’sthermal stress. By using finite element analysis, the thermal stress anddeformation in a single TSV (cylindrical, round table type, Bosch etchingtype) and in a plurality of chip stacked models are studied through the2Dand3D models. Moreover, the effect of different sizes, materials andstructures of TSVs on the thermal stress are also studied. The results provide theoretical foundation and guiding significance for the ICdesigners to design chips with high performance and reliability.Research shows that, in all models with a single TSV, thermalstress in copper-filled TSV is much larger than that in tungsten-filled TSV.The maximum stress occurs at salient points of the deformation, and TSVswith smaller diameters have larger thermal stress. When the TSV depthincreases, the stress trend of cylindrical and round table type are opposite.The round table type TSV is more suitable for models which have highaspect ratios and big difference between the upper and down diameters. Incontrast, Bosch etching has a great advantage in the drilling technics, butthe stress is significantly larger than that with smooth via walls, especiallyin the model with barrier layer (Ti/Ta).The2D transverse profile model is only applicable to study thestress in the central plane and cannot represent the stress at both ends ofTSV. In addition, TSV pitch and arrangement mode will impact the stressand the parameters need to be appropriately chosen. In multiple chipstacked models, selecting appropriate combinations of materials (such assilicon dioxide isolation layer and W-Sn-W bonding, ABF isolation layerand Cu-Sn-Cu bonding) can effectively reduce the thermal stress. As the3D model can visually display the whole deformation in multiple chip stacked models, the relationship between chip size, TSV density and size,chip-stacked numbers and the deformation is studied in detail. The resultsshow that the deformation in multiple chips mainly occurs in the top andbottom die. The deformation is positively related to the chip size, theequivalent CTE in the upper chips and the chip quantity.