Research On ESD Protection Devices Based On SiGe BiCMOS Process

The SiGe BiCMOS process combines the advantages of low cost and high integration of the traditional CMOS process with the excellent radio frequency(RF)performance of the SiGe process,and has been widely used in the millimeter wave and sub-millimeter wave markets.The reliability of integrated circuits under this process has also been paid more and more attention.Among them,the Electrostatic Discharge(ESD)event is one of the important factors that affect the reliability of the integrated circuit.How to improve the ESD protection performance of integrated circuits under this process has become a research focus in this field.This paper is mainly based on TCAD simulation to study ESD protection devices under SiGe BiCMOS process.The main contents are as follows.First of all,the current transport mechanism and ESD protection performance of SCR,OHTSCR(embedded HBT trigger SCR)and NHTSCR(modified OHTSCR)under SiGe BiCMOS process are compared and analyzed.The results show that the SCR trigger voltage is high and the latch-up effect is easy to occur.OHTSCR can effectively reduce the trigger voltage of the SCR,but it will reduce the maintenance voltage,resulting in the device not being able to shut down quickly after the electrostatic event is over,and affecting the performance of the protected circuit.NHTSCR optimizes the maintenance voltage,but it increases the trigger voltage and sacrifices the area of the device.Secondly,two new types of SiGe P+area ESD protection devices are proposed,and the current transport mechanism inside the device is stuied.The introduction of the Ge component in the P+region of the new structure reduces the current gain of the parasitic PNP transistor,weakens the positive feedback effect of the NPN and PNP parasitic transistors,and enhances the anti-latch-up capability of the device.The results show that the new SCR increases the sustain voltage from 2.06V to 10.32V when Ge is uniformly distributed and the Ge content is 30%,which is about four times higher.The new OHTSCR increases the sustain voltage from I.55V to 4.7V when Ge is uniformly distributed and the Ge content is 15%.which is about twice as high.Finally.a new type of groove structure OHTSCR is proposed.This novel dev ice improves the electric field distribution inside the HBT by introducing a groove structure in the shallow trench isolation oi' the collector area.As a result,the current discharge capability is improved,and the positive feedback effect occurs early,resulting in a decrease in the trigger voltage of the device.At the same time,the sustaining voltage remains basically unchanged,and the occupied area of the device is not increased.The results show that.compared with conventional devices,the groove structure OHTSCR reduces the trigger voltage from 8.88V to 5.08V.which is about 43%lower,and the ESD design window is reduced to about 48%of conventional devices.