Design And Research Of Serial-Parallel Hybrid Bus Structure For Heterogeneous Multiprocessor SoC

In recent years,with the increasing integration of heterogeneous multiprocessor SoC,the communication requirements between a large number of processor cores and functional units put forward higher requirements for onchip bus system.At present,the on-chip bus mainly adopts parallel transmission mode,which improves the bandwidth by increasing the bus width and the bus clock frequency.However,with the increase of clock frequency and bit width,the problem of signal offset and signal interference becomes more and more serious,the timing synchronization between parallel signals becomes more and more difficult,and the difficulty of wiring is greatly increased,which prevents the further improvement of the speed of parallel bus.Aiming at the problems of traditional parallel buses with complicated wiring and limited bandwidth improvement,this paper uses the characteristics of high bandwidth and less wiring resources of serial buses,and proposes to apply it to high bandwidth data transmission on chip.Through the design of behavior level and system level serial bus structure on chip,the benefits of serial transmission mode in high-speed data communication on chip are studied prospectively.According to the different characteristics of processor cores and functional units in heterogeneous multiprocessor SoC,this paper designs a serial-parallel hybrid bus structure with low delay parallel bus and high bandwidth serial bus.This structure can greatly improve the on-chip bus bandwidth and match the transmission requirements in heterogeneous multiprocessor SoC.In order to achieve the matching process,the paper has developed arbitration strategy for serialparallel hybrid bus.Serial-parallel hybrid bus is suitable for applications with high bandwidth requirements.In this paper,taking the image neural network data set as an example,we study the practical application of serialparallel hybrid bus,and use the serial bus in the hybrid bus to eliminate redundant bit width and reduce redundant information,and improve the throughput of the serial bus by applying the data coding method to the serial bus.Based on Xilinx FPGA platform,this paper builds the series-parallel hybrid bus system and verifies its function,and evaluates the resource utilization and delay information of the series-parallel hybrid bus system.This paper designs an arbitration allocation strategy for a serial-parallel hybrid bus,and evaluates the transmission time under both static allocation and dynamic allocation.The dynamic allocation strategy can reduce the transmission time by 81.8% at most,and the static allocation strategy can reduce the transmission time by 67% on average.This paper evaluates the resource overhead of Huffman codec module and analyzes its compression efficiency for different data sets.For MNIST data set,the compression ratio is 59.18%,for Fashion MNIST data set,the compression ratio is 30.27%.The comprehensive experimental results show that the serial bus is suitable for high bandwidth transmission applications with low delay requirements.The arbitration method designed in this paper can meet the transmission requirements of heterogeneous multiprosessor SoC,and the dynamic allocation strategy is more efficient.Applying the coding method to the serial interface can effectively improve the throughput of the serial bus,and the Huffman coding is suitable for for compressing grayscale image data sets which have large background area.