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Research On Ldpc Encoding And Decoding Algorithms And Its Quantitative Analysis

Posted on:2010-08-22Degree:MasterType:Thesis
Country:ChinaCandidate:D LiFull Text:PDF
GTID:2198360332957903Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Low Density Parity-Check (LDPC) code has better decoding performance and higher decoding throughput comparing to Turbo code. Its excellent performance makes LDPC code become an optional channel code of IEEE802.16e standard. LDPC code in IEEE802.16e standard is an architecture-aware LDPC code and is created by circular right shift based on some base matrixes. These features make LDPC codes'encoder and decoder based on IEEE802.16e standard much simpler and have higher parallel degree and decode throughput.Based on the research of IEEE802.16e standard and traditional encoding algorithm deeply, two kinds of predigested encoding algorithms are proposed. Some decoding algorithms including Belief Propagation (BP) decoding algorithm in probability domain, Log-domain and likelihood ratio domain, Min-Sum decoding algorithm and modified Min-Sum algorithms are proved on the base of understanding massage passing algorithm. At the same time, the performances of these algorithms are compared. Furthermore, by theoretical analysis and simulation, quantization decoding of LDPC codes and three different hardware implementation architectures (full parallel architecture, partly parallel architecture and full serial architecture) are studied. The simulation results show that if the offset is reasonable (α=0.3), the bit error performance of modified Min-Sum algorithm in waterfall area is almost the same as that of Log-BP algorithm and it can reduce the error floor of the Log-BP algorithm by almost one order of magnitude at high signal-to-noise ratio (SNR), but its decoder complexity is far less than that of Log-BP algorithm. The convergence speed of serial decoding is about two times faster than that of the parallel decoding algorithm, but its decoding speed is slower. To resolve the conflict, partly parallel decoding algorithm is presented which makes hardware implementation possible. Corresponding to the three different hardware architectures, their quantization decoding schemes are proposed which can greatly reduce the decoding complexity with a little performance loss. In a word, the partly parallel modified Min-Sum algorithm is the main investigative direction.
Keywords/Search Tags:LDPC codes, Encode, Decode, Serial schedule, Parallel schedule, Partly parallel schedule, Quantization
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