Design Of A 2.45GHZ Power Amplifier Based-on 0.28?m SOI CMOS Technology

The efficiency of a power amplifier has a substantial impact on the entire system for it consumes a major part of the overall power consumption of an RF front end.However,complex modulation schemes with higher bandwidth efficiency are utilized,imposing even more stringent linearity requirements on power amplifier.As a result,the designing of power amplifiers with high efficiency,high linearity and relatively low price technology becomes increasingly challenging.The SOI technology has lower substrate loss,lower noise cross-talk through substrate,better isolation between devices,no latch-up effect,greater integration capability in RF systems and relatively low price and so becomes a promising candidate for RF power amplifier.A two-stage class-AB power amplifier with an operating frequency range of 2.4?2.4835GHz and a supply voltage of 2.5V is proposed based on 0.28?m SOI CMOS.The power amplifier is biased at class-AB mode to achieve the best trade-off between efficiency and linearity.The first stage is biased at almost class-B mode to further improve the efficiency while the second stage with a dynamic bias is biased at near class-A mode to achieve both good linearity and efficiency.The dynamic bias circuit automatically detects the output power of the driver stage and then sets an adaptive bias current to the output stage accordingly.The two stages can compensate each other in terms of amplitude to preserve a relatively constant power gain in a wider input power range,improving the output compression point as a result.Cascode structure is chosen for its good isolation property,higher voltage handling capability and high output resistance and eventually higher output power and better efficiency.In order to overcome the low breakdown voltage in CMOS technology,RC self-biased architecture is adopted to bias the common-gate transistors,which ease the voltage requirement of the drain terminal so that the output power can be raised.Bias circuits with temperature compensation for the common-source transistors are proposed,helping the PA to achieve the requirement in a temperature range from-40°C to 85°C.Conducted in Cadence Spectre RF environment,the post-simulation results show that,in full temperature range and under all MOS process corners,the minimum OP_{1d B} reaches 18.43d Bm with a PAE of 38.25%at FF 85°C,and maximum OP_{1d B} of 20.31d Bm is achieved at TT-40°C;maximum PAE of 49.21%is achieved at both TT-40°C and SS-40°C;the minimum S21 is 24.59 d B at SS 85°C and the maximum S21 is 28.82 d B at SS-40°C.The PA's total layout area is 880?m×850?m.The performance of the proposed 0.28?m SOI CMOS RF power amplifier meets the design specifications.After test and verification,the chip can be applied to the transmitting front end of the wireless communication system.