Research On High-Efficiency CMOS RF Power Amplifier

With the rapid development of wireless communication technology,the requirements of RF technology are more stringent.RF power amplifier is the most energy-consuming part of the transmitter system,affecting the overall performance of the system.The employment of various high peakto-average ratio modulation signals calls for a high efficiency operation in RF power amplifiers under the power back-off condition,which has become a research hotspot.In this paper,the CMOS Doherty RF power amplifier is presented.First of all,the research background of RF power amplifier,its current research situation at home and abroad and the merits and drawbacks of CMOS process are introduced and analyzed.Then the main performance indicators,classifications and techniques of improving power amplifiers' efficiency are expounded.What is more,the design methods of conventional power amplifiers and the principle of Doherty power amplifiers are theoretically analyzed.This paper lays emphasis on the implementation of the proposed Doherty power amplifier in TSMC 0.18 um process.The self-biased Cascode configuration is used in power transistors of Doherty two-path power amplifier.The RC circuit,which is connected in series between the gate and drain of the Cascode transistor,is used to filter and reduce the voltage swing of the gate-source,so as to alleviate the hot carrier degradation effect and prevent the voltage breakdown.In order to ensure the stable operation of the power amplifier at all frequencies,the negative resistance,K value and stability circuit are analyzed.The RF Choke of each power transistor is achieved by the off-chip ?/4 transmission line.However,the ?/4 transmission lines in the main path to achieve the impedance transformation and in the auxiliary circuit to achieve the phase compensation and input matching are replaced by lumped elements.The simulated K value greater than 1 at all frequencies is verified in Cadence.The power amplifier has achieved 24.52 dBm at the 1-dB compression point and provided 26.46 dB of power gain.IMD3 is expressed for linearity and shows a variation of-30 dBc to-13 dBc under the back-off operation.The main sources of nonlinearity,caused by gate-source capacitance and drain-source current,are discussed in section 4.4.The power added efficiency at 1dB compression point is 39.8%,and PAE at 6dB back-off is still 24.86%.Compared to the Class AB power amplifier,an obvious enhancement of efficiency can be observed under the back-off operation.Besides,summarization and comparison of the reported CMOS Doherty power amplifiers are made in the end.