Hybrid Scratchpad And Cache Memory Management For Energy-efficient Parallel HEVC Encoding

The next-generation video coding standard High Efficiency Video Coding (HEVC/H.265) is capable to provide high resolution videos at double compression compared to the widespread Advanced Video Coding (AVC/H.264) standard. Several novel coding techniques have been adopted to improve the compression and parallelism of HEVC, including variable block size, multi-level filtering, and independently processed video tiles. However, these new features not only lead to significantly heavy computation workload, but also requires 2X more demand on total memory accesses compared to H.264/AVC. Therefore, memory subsystem optimization is of paramount importance to support HEVC on resource and energy constrained embedded consumer electronics.In this paper, we present a hybrid on-chip memory architecture with both caches and scratchpad memories (SPMs) for high performance and energy efficient HEVC on multi-core platform. A run-time prediction algorithm is proposed to effectively identify the most frequently accessed memory regions in the search window(s) for processing individual coding tree units (CTUs). Depending on their intra-and inter-core reuses, these regions are loaded into the private or shared SPMs for guaranteed on-chip memory accesses. On the other hand, a relatively small hardware-controlled cache is used for the rest of data accesses.The hybrid video memory management unit (HVMMU) is proposed to translate a virtual memory address into the corresponding SPM address if the accessed data is prefetched into SPM. Furthermore, when each time an address translation is performed, we record the access count of the corresponding load window in the hardware logic, which provides the history access behavior information for load window prediction algorithm. In order to further reduce the leakage power of the on-chip SPM, we design a power gating control algorithm which predicts the less-frequently accessed load windows in the SPM, and selects an appropriate low-power state for the corresponding SPM sectors based on the history load window access behaviors.We have implemented the load window prediction algorithm and power gating scheme in the HEVC test model HM 14.0 and the hybrid SPM-Cache memory architecture and power gating control in gem5 simulator. We evaluate the performance and energy consumption of the proposed hybrid video memory architecture and the memory management. Compared with the state-of-the-art solution, experimental results illustrate that our proposed memory management framework supports high speed parallel HEVC processing with substantially smaller total on-chip memory size, which achieves up to 76.23% on-chip leakage energy savings, and 33.31% energy saving for the overall memory subsystem.