Research On Spatially Coupled LDPC Codes And FPGA Implementation

Compared with ordinary low-density parity-check(LDPC)codes,spatially-coupled LDPC codes have excellent decoding performance and lower decoding complexity due to the special structure.However,in the two traditional decoding methods of spatially-coupled LDPC codes,either the requirements of storage resource are too large,or the parallel computing is not supported.Therefore,this thesis aims at low storage requirements and parallel computing,and studies the decoding methods of spatially-coupled LDPC codes,and presents the field-programmable gate array(FPGA)implementation of decoders based on different decoding methods.First,in order to reduce storage requirements and support parallel computing,a hybrid decoding method is proposed.The new decoding method is based on the sliding window decoding method,adopts pipeline operation technology to reorganize the messsage update sequence,and adopts compact storage management.The hybrid decoding method has the characteristics of low storage requirements,and supports for parallel computing,which is beneficial to increase decoding throughput and reduce decoding delay.Second,in order to implement the decoder based on the sliding window decoding method on the FPGA platform,the implementation adopts the following technology.The implementation stores information about the parity-check matrix in a read-only memory so that the configuration can be read in real time,thereby increasing flexibility.The implementation adopts a partial parallelism structure to process multiple information at the same time(the degree of parallelism is equal to the expansion factor),thereby improving decoding throughput.The implementation adopts the design of ring memory to accelerate the speed of data movement,thereby improving the decoding speed;The implementation adopts the scaled min-sum algorithm to simplify the message updates and reduce computational complexity.Third,for the FPGA implementation of the decoder based on the hybrid decoding method,the main difference lies in the use of multiplexers on the memory so that the control signal can read(or write)the corresponding data block,thereby supporting multiple processors work at the same time and processing more message(the degree of parallelism is equal to the expansion factor multiplied by the number of processors).At a clock frequency of 150MHz,the throughput of hybrid decoder with 7 processors and 1 iteration can reach 278Mbps,which is about 6.1 times that of sliding window decoder,while maintaining the same computational complexity and performance,and consuming less storage resource.