Research On Some Key Techniques In The Design Of Coarse-grained Dataflow Network Processor

With the rapid development of the Internet, social communities have shown an increasing reliance on the network. The continuously emerging network applications and services pose even higher requirements to the network processing equipments. Network processing equipments should have high-speed processing capability to meet the requirements of the growing network traffic and bandwidth. Moreover, they should have the flexible protocol processing capacity and efficient programmability to support rapid configuration and deployment of new services and applications, so as to effectively reduce the design turnaround time of network products. Network processors have emerged as core components of next-generation Internet to address the above requirements, and they are rapidly and widely applied to the Internet infrastructure.Novel network processor architectures should be put forth to accommodate the streaming nature of processing networks traffics, so as to overcome the shortages of processing model and fixed topologies in traditional control-flow network processors. Based on coarse-grained dataflow computing model, this paper presents a novel coarse-grained dataflow network processor DynaNP, along with the key technologies involved in the design of DynaNP. The major contributions and innovations of our work include:To meet the programmability, performance and adaptability requirements of the network processing equipments in edge/access network, a novel coarse-grained dataflow network processor DynaNP is proposed. DynaNP is designed based on the coarse-grained dataflow computing model. By introducing the control-flow structure into the design of processing engine (PE), the programmability of the system can be effectively improved. And, task parallelism in network applications can be effi-ciently explored by taking advantage of the coarse-grained dataflow approach. The micro-architecture, token-driven packet processing model and function/structure of key processing components in DynaNP are introduced based on the systemic sum-mary in the architectural features and concepts of DynaNP. By integrating a wealth of hardware-accelerated resources and flexible global scheduling resources, the per- formance for processing packets and the adaptability to the dynamic network traffic of DynaNP can be effectively improved.To exploit hardware acceleration resources in DynaNP, an automatic synthesis mechanism for hardware acceleration resource-DynaHB is proposed. And, the core selection algorithm of hardware acceleration resource is designed and imple-mented. DynaNP integrates a large number of hardware acceleration resources, including various co-processors and optimized custom instructions, to speed up the system processing performance, while DynaHB can provide effective guidance to the deployment of the hardware acceleration resources integrated in DynaNP. Ex-perimental results show that, the mechanism can be customized for the hardware acceleration resources with different-scale, to quickly determine the approximate optimal configuration of hardware acceleration resources.Aiming at the custom-instruction extension problem of DynaNP, two exact algorithms for custom-instruction identification-ConsEnum and RelaxEnum are proposed. Custom-instruction extension is a key point in DynaHB, as it need to cope with the huge search space and different micro-architecture constraints. Under given register-port constraints of PE, ConsEnum can quickly enumerate all valid instances of custom instructions by adopting simple and efficient pruning strategies, which can greatly reduce the search space. Aiming at the problem with relaxed register-port constraints, RelaxEnum algorithm is able to quickly obtain the exact solutions, by adopting top-down manner for iteratively dividing the problem. Experimental results show that the performance of the two algorithms is generally superior to the algorithms dealing with the same problems, under the promise of obtaining the optimal solutions.To effectively exploit the global scheduling resources of DynaNP, processing resource allocation and scheduling mechanism DynaRS is proposed, which contains two algorithms, i.e, TPRSA and TPPDS. TPRSA is used to optimize the mapping from the tasks in the network applications to the processing resources of DynaNP, while TPPDS is responsible for dynamically adapting the network traffic workload on the PEs of DynaNP. Simulation results show that, DynaRS can ensure load balance of the system and avoid unexpected performance jitter brought by boosted network traffic, thus to effectively improve the throughput and packet forwarding rate of DynaNP.Lastly, the resource development platform DynaPF is introduced. DynaPF is composed of the tool chain DynaHBtool and the simulator TPS, which provide support for the exploration of DynaNP resources. DynaHBtool and TPS are respec-tively used to support the automatic synthesis mechanism of hardware acceleration resource and the performance evaluation of resource allocation and scheduling mech-anism. DynaPF are partially developed independently and partially by extending the existing tools.