Design On Embedded Security Coprocessor

With the rapid development of embedded information security, how to implement these cryptographic algorithms effectively and fast has become a more prominent issue. There are two traditional way to implement encryption algorithm:one is to use program via a general purpose processor, although this approach has better adaptability and flexibility, but it has a low efficiency; another is to use ASIC for special encryption algorithms, although the performance has been improved, but it is high cost and has a low flexibility. Therefore, this paper proposes an embedded co-processor based on cryptographic algorithms instruction set. This solution has strong adaptability and high performance when dealing with a cryptographic algorithms. Experiments show that the processing performance is improved by about three fold in the simulation platform and the FPGA platform, with a relatively good acceleration effect.With the rapid development of cryptography, Attack mode of encryption chip is also endless, so in the process of designing a secure coprocessor, we should not only pay attention to improve performance, but also pay attention to the prevention of various attacks. In this paper, propose two solutions are proposed to deal with the differential power analysis, which is very common in recent years, by interference the power track in timeline when program runs. One is based on random delay insertion, the other is based on random instruction insertion. The experiment shows this architecture has a good ability to resist the differential power analysis attack. The solutions proposed in this paper can be realized easily, and have not complicated hardware architecture, so it has major practical value comparing with traditional anti-differential power analysis solutions.