Design Of Extensible External Bus Interface On DSP Based On AXI Bus Protocol

With the rapid development of social informatization,people have higher requirements for Digital Signal Processor(DSP)performance,and multi-core architecture has become the main trend of development.The External Bus Interface Unit(EBIU),as the bridge between the internal processor of a multi-core DSP and external devices,occupies a pivotal position in DSP design.At present,most domestic manufacturers use traditional EBIU design,and traditional EBIU applies distributed arbitration to realize the sharing of external bus resources by DSP processors.There are problems such as poor multi-core DSP scalability and large arbitration power consumption in traditional EBIU.Therefore,it is necessary to design an external bus interface with strong scalability and low arbitration power consumption to meet the requirements for flexibly expanding the core number of multi-core DSPs.This paper first addresses the problem of large power consumption of traditional multi-core DSP arbitration.Through a comparative analysis of distributed arbitration and centralized arbitration schemes,we propose an architecture of an external independent request arbiter to simplify the arbitrate signal of each core in multi-core DSP,and introduce it into a separate module for arbitration operations.The scheme reducing arbitration power and hardware resource effectively.Secondly,in order to solve the problem of poor scalability of multi-core DSP,this paper optimizes the round-robin arbitration method and proposes a scalable round-robin arbitration mechanism.This mechanism enables the DSP processor to participate in the sharing of external bus resources only by providing a request signal,which improves the scalability of the multi-core DSP.Finally,we analyse the interface signals and characteristics of EBIU comprehensively,then design functional modules including SDRAM controller,register configuration module and data buffer.At the same time,we design a scalable external bus interface suitable for multi-core DSP based on the AXI bus protocol.This article uses Verilog HDL language for RTL level hardware implementation,and adopts UVM to build a verification platform,complete the functional simulation of each module of EBIU,and achieve 100% functional coverage.Then verify the FPGA based on the Quartus platform.Based on the TSMC90 nm process,this paper completes the synthesis by DC,completes the place and route by ICC.Compared with the traditional EBIU,this design enables multi-core DSPs to increase cores flexibly,and increases the maximum number of cores to 16,which make multi-core DSPs have stronger scalability.Through thecomprehensive simulation test,this design reduces the dynamic power consumption of the arbitration system to 201 ?W.And it has higher arbitration efficiency under the rule of round-robin arbitration.