Design And UVM Verification Of High Stability External Bus Interface On DSP Chip Based On AXI Protocol

Today in the digital age,multi-core DSP chips are widely used in the market.Among them,the external bus interface unit(EBIU),as a module connected to the external bus in the multi-core DSP chip,plays an important role in the arbitration and data interaction of the external bus.When DSP is running,multiple cores often have to work together.The arbitration mechanism in EBIU solves the resource allocation problem of the external bus.Traditional EBIU mostly uses a simple distributed arbitration mechanism.As the number of cores increases,the probability of bus arbitration errors also increases.Therefore,designing an EBIU with a high error-tolerant error correction mechanism is of great significance to the development of the later DSP chip multi-core.Aiming at the problem of insufficient external bus arbitration stability in multi-core DSP,this paper proposes an arbitration error correction mechanism by analyzing and comparing the traditional EBIU arbitration architecture to make the judgment result of the external bus more accurate and effectively reduce the operation failure caused by arbitration.Secondly,based on the polling priority arbitration algorithm,the design of the arbitration module is completed,which further enhances the accuracy of arbitration in the multi-core DSP and optimizes the allocation of external bus resources.Combining the arbitration error correction module,based on the EBIU interface protocol,a series of components such as AXI interface module,external bus interface module,and SDRAM controller are designed to complete the design of EBIU.Aiming at the problem that it is difficult to verify the arbitration scene,the verification platform was built based on the UVM methodology.Based on verification technologies such as SVA(System Verilog Assertion)and CDV(Coverage Driven Verification),a large number of specific incentives are used to simulate multiple arbitration scenarios to complete the functional verification of the designed EBIU code.This article uses Verilog HDL language to complete the RTL design of EBIU,and uses UVM verification methodology to build a verification platform,and completes the verification of the EBIU design code on the Questa Sim software platform.The final function coverage rate reaches 100%,fully verifying the functional integrity of the designed code.After that,FPGA prototype verification was performed on the QUARTUS II platform,DC synthesis and ICC layout were performed in the SMIC180 nm CMOS process environment,and layout and back-end timing analysis were completed.Compared with the traditional EBIU,the stability is improved by about 10% under normal circumstances,and the error-correction tolerance is improved by about 53% in sudden situations.The overall operational stability has been greatly improved.