The Parameterized Design And Verification Of The On-Chip Ring Interface InM-dSP

With the rapid increase of the digital information processing requirements, the on-chip multi- core digital signal processor has become main development trend of the high performance DSP. Compared with traditional bus connections, Network on chip(NoC) has the great advantages on high efficiency,scalability and reusability. It has become the main method for the multi-core DSP interconnection. Between the NoC and network node,the network interface is responsible for their connection and influences the NoC communication performance and efficiency. How to design a correct,high performance, reusable on-chip network interface has become a focus in NoC researches and designs. Based on the on-chip no-blocking ring network architecture of the high-performance multicore digital signal processor—M-DSP developed independently by National University of Defense and Technology, this thesis has designed and implemented its ring network interface and carried out the full functional verification. The main points and works of this thesis are as follows:1?Based on the analysis of the M-DSP overall architecture and the design needs of its ring network, the overall design scheme of the ring network interface(RNI) for the six DSP super nodes has been put forward. The parameterized RNI design based on its super node position has been realized, which could realize the reuse of RNI design code on the DSP super nodes and greatly reduce the front end design and code maintenance, the back-end physical design workload and accelerate design speed.2?According to the multi- level, multi- link structure of the ring network and node access requirements, the ring network arbitration controllers for the bidirectional data read/write and single direction configuration of ring network have been implemented and ensured all the ring requests transfer correctly, fair and orderly.3?In order to support non-blocking ring network structure and the interface data bandwidth matching requirements, the input and output FIFO controllers for request link and return link haved been designed, which can realize continuous transmission for data read and write link layer of the ring, resolve the deadlock and head blocking problems of data transmission, and ensure the normal and continuous data transmission..4?based on the System Verilog language, the module level testbench for function verification has been established, in which the malibox, samphore, queue, assertions and other senior verification technologies are used. A constrained random stimulus generator and automatic checker have been realized, which greatly improve the verification efficiency. The verification result has shown the function of RNI be correct and obtain nearly 100% code coverage.5 ?Based on the 40 nm technology and 1GHz working frequency constraints, the logic synthesis and optimization have been implemented by logic synthesis tool. The result has shown the RNI design satisfy the timing requirements of M-DSP.