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Research Of Improving Address Translation Performance By Die-level Balanced Data Layout In Flash-based SSDs

Posted on:2021-12-01Degree:MasterType:Thesis
Country:ChinaCandidate:J LiFull Text:PDF
GTID:2518306104487974Subject:Computer system architecture
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Flash-based solid state drives(SSDs)has been widely deployed in consumer and enterprise storage markets due to high performance and low latency.Address mapping algorithm that translates logical page number(LPN)to physical page number(PPN)is one of the factors that affect the performance of SSD.With the aggressive scale-out of SSD capacity,the growth rate of RAM doesn't catch up with that of SSD capacity for the influence of price,process,power consumption and reliability.RAM becomes in short supply,Which leads to more cache miss with overmuch mapping entry replacement and gravely degrade performance.How to increase the cache hit rate of mapping cache with limited RAM becomes a key issue to be solved urgently for SSD.There are two direct factors that affect the mapping cache hit rate: the address mapping algorithm and the maximum number of cached mapping entries.Traditional approach to increase cache hit rate of mapping cache usually seek for better address mapping algorithms via log-buffer/workload based varied-granularity mapping schemes or utilizing temporal locality to cache frequently-access mapping entries,but all the traditional methods can not increase the maximum number of cached mapping entries.This paper proposes an address mapping algorithm called Thinmap based on Die-level balanced data layout,which increases the maximum number of cached mapping entries by relieving the RAM cost of each mapping entry.Based on the superpage-level data allocation,Thinmap allocates each LPN across all dies with same offset to make all PPNs armed with the same offset address fields.By only keeping the same offset address field,Thinmap can efficiently downsize RAM overhead of each mapping entry and cache more mapping entries to greatly increase cache hit rate.As for Die-level balanced data layout,each LPN is distributed to all Dies,one read operation becomes multiple read operations across all Dies,which leads to read amplification,Due to temporal locality and spatial locality,Thinmap employs a read prefetch technique to reduce read operations and relieve read amplification.Comprehensive experiments based on SSDsim are carried out with various real-world workloads.Results show that the Thinmap improves system performance(IOPS)up by 48.6% compared to DFTL.
Keywords/Search Tags:NAND Flash, SSDs, Address Mapping, Superpage, Mapping Entries, Data Layout
PDF Full Text Request
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