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Memory Data Management Algorithm Research Of Embedded System Based On NAND Flash

Posted on:2014-07-23Degree:MasterType:Thesis
Country:ChinaCandidate:H XiaoFull Text:PDF
GTID:2268330425972368Subject:Electronics and Communications Engineering
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Abstract:The mass data in the conference auxiliary-support system demands for high-performance of the embedded terminal. In particular, the embedded terminal needs to read and write large amounts of data quickly, and ensure high data reliability. There are some problems to use Flash memory chips in embedded systems, such as imbalance of reading and writing, out-of-data update. Data Management is necessary to this kind of system.The thesis proposes a replacement algorithm based on the hot priority, and proposes the two cache mapping granularity exchange FTL (Flash Translation Layer) algorithm-CEFTL. Flash memory is divided into data block and translation block in algorithm CEFTL. Page mapping table is stored in the translation block. Address mapping is divided into block mapping and page mapping. The two different particles are exchanged through the Global Translation Dictionary (GTD), so as to improve the cache hit ratio.We improve the algorithm LRU-WSR based on the hot detection algorithm. According to the different frequency and storage characteristic of data access to the NAND flash memory, the logical data block is divided into four different priorities to build the two-level replacement algorithm. The two-level replacement algorithm is used to solve the replacement cost of the particularity of data access to the NAND flash memory.Based on the two-level replacement algorithm, the mapping algorithm of CEFTL is proposed to solve the lack of reliability and wear-leveling in RFTL. It changes the page mapping of hybrid map storage location so that the OOB(Out of Band) can be stored longer ECC code and improve reliability of system. The algorithm CEFTL uses the two cache mechanism in CDFTL. As a result, RAM space consumption is reduced. To improve switching operations and shift operations of the distributed garbage collection strategy in RFTL, we add the dimension of heat which exchange the hot and cold blocks. As a result, it makes the erase count of the physical block with different access frequency closed in the real-time system. The average system response time in CEFTL is closed to optimal response time in RFTL by priority-replacement policy.
Keywords/Search Tags:embedded system, NAND Flash, address mapping, two-levelcaching mechanism, hot power, FTL
PDF Full Text Request
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