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Research And Implementation Of Key-Value-Based Flash Translation Layer For Large Scale SSDs

Posted on:2018-01-20Degree:MasterType:Thesis
Country:ChinaCandidate:J LiFull Text:PDF
GTID:2428330623450620Subject:Computer Science and Technology
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With the popularity of computers and computer networks,digitization has become an important feature of the contemporary world.Advances in processor technology have led to significant improvements in computing performance,and breakthroughs in storage technology research have provided the basis for hardware assurance of mass data storage.According to IDC,computer performance and data volume are in accordance with Moore's Law growth.With the advent of data-intensive applications and the advent of big data times,the amount of data has reached the PB level.Large data sets impose very high demands on memory technology and storage capacity,and place stringent requirements on the overall performance of storage devices such as read and write performance,lifespan,reliability and bandwidth.Traditional storage architectures often use a hard disk array,but due to the limitations of their internal mechanisms,they suffer from poor read speed,data transfer bandwidth,performance,and power consumption when dealing with large amounts of data.In the era of big data,the entire computer system has higher and higher requirements on the storage subsystem.The traditional disk array storage system can not meet people's increasing storage needs in terms of delay,bandwidth,power consumption,etc.,and based on the new storage technology,enhancing the performance of the entire storage array has become a hot research topic.Based on this demand,a large number of NAND flash devices,phase change memory(PCM),magneto resistive random access memory(MRAM),ferroelectric random access memory(FRAM),Memristor(RRAM)as the representative of the new storage media.Among them,flash array-based SSDs are superior to traditional disks in many aspects due to their low price,high bandwidth,fast reading and writing speeds,nonvolatile and low power consumption.However,due to the fact that flash memory itself has out-of-place update property that are different from traditional disks,the traditional flash memory controller can implement address mapping and use a flash translation layer to use the solid state disk in a disk-based manner.Large-scale array subsystems made up of SSDs are designed to meet the bandwidth requirements of large-scale arrays.However,due to its design flaws in the internal flash memory translation layer,it cannot meet the read / write performance requirements of the application and greatly reduce the lifetime of the flash memory array.With the emergency of 3D TLC/QLC NAND flash,the capacity of flash-based SSD is growing rapidly,from hundreds of gigabytes to tens/hundreds of terabytes.The Flash Translation Layer(FTL)within such a large SSD confronts with serious problems that have not appeared ever before.Traditional FTLs either adopt coarse-grained mapping mechanism thus facilitate the mapping table to be kept in DRAM completely,or adopt fine-grained mapping mechanism but only keep frequently accessed mapping information in DRAM depending on the locality of workloads.Whereas,we argue that both of the above policies are unsuitable for SSDs supplying ultra-large capacity.On one hand,the large SSDs introduce into so much more mapping entries than ever that even the coarse-grained mapping mechanism cannot produce an enough compact mapping table to be kept in DRAM completely.On the other hand,the large SSDs tend to be deployed in data centers to serve for IO requests from massive users under various application backgrounds,where these IO requests exhibit weaker spatial and temporal localities.As a result,the method that keeps frequently accessed mapping information in DRAM is impractical for large SSDs as well.In this paper,we propose a novel KV-FTL for large scale SSDs,which mostly maps logical addresses to physical addresses via a simple hash function,while handles hash confliction and out-of-place data update by the traditional manner,i.e.,the mapping table.Our KV-FTL is able to accelerate address translation by avoiding loading mapping table from flash memory to DRAM,thus improve performance;as well as reduce the write-traffic introduced by the mapping table,thus extend the lifespan of SSDs.To the best of our knowledge,this is the first time to apply key-value principle into FTL design.This paper mainly studies and realizes the Key-Value-based flash conversion layer of large-scale flash array based SSDs.The main work is as follows:First of all,this paper studies the storage characteristics of flash memory,the internal structure of the SSD,and a detailed investigation of the current research status of the flash translation layer.We put forward the research background and research motivation of this research topic,and clarified the problems to be solvedSecondly,aiming at the problem of low read and write performance and long lifespan reduction of current flash memory translation layer,a new type of flash memory conversion for large-scale flash-based solid-state disks is designed by combining the current research on Key-Value stores and the key-value concept Layer,and put forward its design concept,describing its design architecture.Corresponding algorithm is detailed.Thirdly,in this paper,the current FTL scheme proposed an architecture optimization scheme-the use of flash memory array internal channel-level parallelism.Finally,this paper studies the development trend of the current mainstream key storage system,focuses on the key optimization points and the corresponding technologies used,and puts forward the prospect of future research.At the same time,this paper takes [51] as the prototype,and based on this(note that the configuration is based on an issued SSD,with 1TB capacity and 512 MB DRAM),implements the architecture,designs and implements the flash-based high capacity SSD and the corresponding key-based flash translation layer.Experimental results show that our KV-FTL facilitates SSDs to survive longer lifespan by a factor of up to 18.7% with an average of 13.6%;improves read performance ranging from 18.4% to 50.7% with an average of 39% with optimization,and in the case of extremely intensive requests,improves the access performance for requests with an average of 60%.
Keywords/Search Tags:key-value, flash memory, SSD, FTL, channel-level parallelism, address mapping table, lifespan, performance
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